Index: README_USRP_QPSK_examples.txt =================================================================== --- README_USRP_QPSK_examples.txt (revision 0) +++ README_USRP_QPSK_examples.txt (revision 0) @@ -0,0 +1,289 @@ +Quick overview of what's here: + +Go to gnuradio-examples/python/qpsk_fpga + +These are special versions of qpsk RX and TX benchmarks which use modified usrp fpga firmware with built-in RRCfilter, fractional interpolator and qpsk modulator. + +* commandline_tx_*.sh : example commandline for tx +* commandline_rx_realtime*.sh : example commandline for rx (realtime) +* commandline_rx_file*.sh : example commandline for rx (first prerecording, then demodulating) + +The python scripts which do the real work: + +* benchmark_tx_qpsk_fpga.py: generates packets of the size you +specify and sends them across the air using the USRP. +It uses special fpga firmware with built-in RRC filter, fractional interpolator and qpsk modulator. +The firmware filename has to be given on the commandline with -F firmwarefilename.rbf + +The excess-bandwidth (alpha) and interpolation factor are hardcoded in the firmware. +There are four firmwares: +The total interpolation_rate=DAC_interpolation*interpolation/decimation +the number of symbols/sec is determined by the interpolation_rate and DAC samplerate +DAC_samplerate=128 Msamples/sec +symbols_per_sec=128.0e6/interpolation_rate +bitrate=2*symbols_per_sec for qpsk +usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec10_DACint4X.rbf bitrate= 40Mbit/sec, alpha=0.2 +usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf bitrate= 4 Mbit/sec, alpha=0.2 +usrp_frac_interp_2rxhb_2tx_alpha0.35_int16_dec10_DACint4X.rbf bitrate= 40 Mbit/sec, alpha=0.35 +usrp_frac_interp_2rxhb_2tx_alpha0.35_int16_dec1_DACint4X.rbf bitrate= 4 Mbit/sec, alpha=0.35 + + +fpga_filename="usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec10_DACint4X.rbf" + +This particular example uses a firmware with +2 rx channels +2 tx channels +alpha=0.35 +interpolation=16 +decimation=1 +(so interpolation_rate=16/1=16.0) +DAC interpolation=4X +(so total interpolation=4*16=64) + +This results in a bitrate of +bits_per_symbol*DACRATE/(DAC_interpolation*(interpolation/decimation)) +=2*128000000/(4*(16/1))= 4 Mbit/sec +(qpsk has 2 bits_per_symbol) + +If you change the line with the fpga_filename to usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf +you get interpolation 4*1.6=6.4 and alpha 0.2. +So with this firmware you can send two 40 Mb/sec qpsk streams with alpha 0.2. (one on TXA and one on TXB) + +The script works well using the USRP with the RFX transceiver daughterboards or basic_TX boards. +You can not specify the bitrate. The bitrate is determined by the +fractional interpolation rate of the fpga firmware. +interpolation_rate=4*16.0 => 4 Mb/s +interpolation_rate=4*1.6 => 40 Mb/s + + +You should also pass the interpolation and decimation factor of the hardcoded fractional interpolator as commandline parameter to optimize usb throughput and to show the right bitrate + -IFI_INTERP, --fi-interp=FI_INTERP + give interpolation of fractional interpolator which is + hardcoded in selected fgpa (only used to optimise usb + transfers and calculate bitrate) [default=16] + -DFI_DECIM, --fi-decim=FI_DECIM + give decimation of fractional interpolator which is + hardcoded in selected fgpa (only used to optimise usb + transfers and calculate bitrate) [default=1] + +you should also pass the transmit RF frequency with -f or --freq + -fFREQ, --freq=FREQ set Tx and/or Rx frequency to FREQ [default=%default] + +The output level is determined by the bitshift parameter. +This reduces the output level in the digital domain before samples go to the DAC (so you do lose some resolution) + -bBITSHIFT, --bitshift=BITSHIFT + bitshift range(-15,15) determines the tx amplitude + attenuation, higher values give more attenuation, a too + low value gives overflows and/or distortion in RFX + boards 0=> +6dB 1=>0 dB (tx_amplitude=8192) 1=>-6 dB + (tx_amplitude=4096), 2=> -12 dB and so on. Values 1, 2 + and 3 are good for RFX boards [default=2] + +I added this option because RFX boards get a distortion problem when you use the full output range of the DAC. + +If you use multiple usrps you can specify which usrp to use with -u + -uUSRP, --usrp=USRP which usrp to use (0, 1, 2 ...) [default=0 is the last + one plugged in] +The last usrp plugged in is allways usrp 0, the second last is 1, the one before is 2, and so on. + +You can also select modulation type with the -m commandline argument, +but the only legal value for is dqpsk_fpga which is also the default. + + + + + +for basicTX this works well: +./benchmark_tx_qpsk_fpga.py -T A -f 16.0e6 -m dqpsk_fpga -v -F usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf -I 16 -D 1 +(see commandline_tx_txA_basicTX_alpha_0.2_bitrate_4M_freq_16MHz.sh) + +for RFX900 this should work: +./benchmark_tx_qpsk_fpga.py -T A -f 900.0e6 -v -F usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf -I 16 -D 1 +(see commandline_tx_txA_rfx900_alpha_0.2_bitrate_4M_freq_900MHz.sh) + +To show all commandline options use -h or --help + ./benchmark_tx_qpsk_fpga.py -h +usage: benchmark_tx_qpsk_fpga.py [options] + +options: + -h, --help show this help message and exit + -mMODULATION, --modulation=MODULATION + Select modulation, only dqpsk_fpga is valid for this + script [default=dqpsk_fpga] + -sSIZE, --size=SIZE set packet size [default=%default] + -MMEGABYTES, --megabytes=MEGABYTES + set megabytes to transmit [default=%default] + -fFREQ, --freq=FREQ set Tx and/or Rx frequency to FREQ [default=%default] + -uUSRP, --usrp=USRP which usrp to use (0, 1, 2 ...) [default=0 is the last + one plugged in] + -FFPGA, --fpga=FPGA set fpga_filename to FPGA [default=usrp_frac_interp_2rx + hb_2tx_alpha0.2_int16_dec1_DACint4X.rbf] + -bBITSHIFT, --bitshift=BITSHIFT + bitshift range(-15,15) determines the tx amplitude + attenuation, higher values give more attenuation, a too + low value gives overflows and/or distortion in RFX + boards 0=> +6dB 1=>0 dB (tx_amplitude=8192) 1=>-6 dB + (tx_amplitude=4096), 2=> -12 dB and so on. Values 1, 2 + and 3 are good for RFX boards [default=2] + -IFI_INTERP, --fi-interp=FI_INTERP + give interpolation of fractional interpolator which is + hardcoded in selected fgpa (only used to optimise usb + transfers and calculate bitrate) [default=16] + -DFI_DECIM, --fi-decim=FI_DECIM + give decimation of fractional interpolator which is + hardcoded in selected fgpa (only used to optimise usb + transfers and calculate bitrate) [default=1] + -TTX_SUBDEV_SPEC, --tx-subdev-spec=TX_SUBDEV_SPEC + select USRP Tx side A or B + -v, --verbose + + + + +* benchmark_rx_qpsk_fpga.py: the receiver half of benchmark_tx.py. +Command line arguments are pretty much the same as tx. +make sure you set the modulation to dqpsk with -m dqpsk +You also must set the excess-bandwidth (alpha) explicitely with --excess-bandwidth + +benchmark_rx_qpsk_fpga.py --help shows the commandline options. +Works well with a USRP and RFX transceiver daughterboards, dbs_rx or basic_rx. + +./benchmark_rx_qpsk_fpga.py -h +usage: benchmark_rx_qpsk_fpga.py [options] + +options: + -h, --help show this help message and exit + -mMODULATION, --modulation=MODULATION + Select modulation from: qam64, d8psk, qam16, dbpsk, + dqpsk, gmsk [default=%default] + -fFREQ, --freq=FREQ set Tx and/or Rx frequency to FREQ [default=%default] + -rBITRATE, --bitrate=BITRATE + specify bitrate. samples-per-symbol and interp/decim + will be derived. + -uUSRP, --usrp=USRP which usrp to use (0, 1, 2 ...) [default=0 is the last + one plugged in] + -FFPGA, --fpga=FPGA set fpga_filename to FPGA [default=usrp_frac_interp_2rx + hb_2tx_alpha0.2_int16_dec1_DACint4X.rbf] + -RRX_SUBDEV_SPEC, --rx-subdev-spec=RX_SUBDEV_SPEC + select USRP Rx side A or B + --rx-gain=GAIN set receiver gain in dB [default=midpoint]. See also + --show-rx-gain-range + --show-rx-gain-range print min and max Rx gain available on selected + daughterboard + -v, --verbose + + Expert: + -SSAMPLES_PER_SYMBOL, --samples-per-symbol=SAMPLES_PER_SYMBOL + set samples/symbol [default=%default] + -dDECIM, --decim=DECIM + set fpga decimation rate to DECIM [default=%default] + --excess-bw=EXCESS_BW + set RRC excess bandwith factor [default=%default] (PSK) + + + +example: +./benchmark_rx_qpsk_fpga.py -m dqpsk -R B -f 900.0e6 -F usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf --excess-bw 0.2 -r 4000000 --rx-gain 30 -u 0 +(see commandline_rx_realtime_usrp0_rxB_dbsrx_alpha0.2_bitrate_4M_freq_900MHz.sh) + +use usrp 0 (= the last one plugged in, in this case this is the same usrp as used for tx) +use modulation dqpsk +rf frequency 900 MHz +bitrate 4 Mbit +daughterboard B +verbose +rx-gain 30 dB +alpha 0.2 + +WHen you use seperate usrps for tx and for rx you could use: +./benchmark_rx_qpsk_fpga.py -m dqpsk -R B -f 900.0e6 -F usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf --excess-bw 0.2 -r 4000000 --rx-gain 30 -u 1 + +(see commandline_rx_realtime_usrp1_rxB_dbsrx_alpha0.2_bitrate_4M_freq_900MHz.sh) + +-u 1 use usrp 1 (=the first one plugged in, the last one plugged in is 0 which I use for transmitting in this example. + +You could even leave out the -F usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf in this case. +The receive script can use the standard firmware of the usrp. + +./benchmark_rx_qpsk_fpga.py -m dqpsk -R B -f 900.0e6 --excess-bw 0.2 -r 4000000 --rx-gain 30 -u 1 + +This only fails when you use the same usrp for both transmit and receive. In that case you have to tell the receive script to use the same firmware which is needed for the transmit side. + + +You can also work with basicRX and basicTX daughterboards. +Make sure you set the right gain (-g 10 should work) and connect both I and Q. + +Should also work with basicRX daughterboard with both I and Q connected. +Will also work with TVRX daugherboard, but you'll need to fiddle with the gain. + + + +Special notes: Since the usrp can do only 8 MSPS on receive side, +(or 16 when using 8 bit mode) you cannot receive the 40 Mb/sec which +you can send with benchmark_tx_qpsk_fpga.py when using a firmware with +interpolation_rate 1.6. +You can only receive with firmware with 16.0 interpolation_rate (4Mb/sec). +Most machines are not fast enough for this though. For this I added +benchmark_rx_qpsk_file.py + +This script can demodulate prerecorded streams. +You can record them with +usrp_rx_cfile_basicrxcomplex_fpga.py (for using basicRX daughterboard with both I and Q connected to basicTX) +or +usrp_rx_cfile_fpga.py (for recording with other daughterboards or for only using I on basicRX) + +The following examples first prerecord a stream and then demodulate it. +The recieved raw sample stream of the usrp is saved in data_cfloat.raw +commandline_rx_file_usrp0_rxA_basicRX_freq_16MHz_alpha_0.2_bitrate_4M.sh +commandline_rx_file_usrp0_rxA_basicRX_freq_16MHz_alpha_0.35_bitrate_4M.sh +commandline_rx_file_usrp0_rxB_rfx900_freq_900MHz_alpha_0.2_bitrate_4M.sh +commandline_rx_file_usrp0_rxB_rfx900_freq_900MHz_alpha_0.35_bitrate_4M.sh +commandline_rx_file_usrp1_rxB_rfx900_freq_900MHz_alpha_0.2_bitrate_4M.sh +commandline_rx_file_usrp1_rxB_rfx900_freq_900MHz_alpha_0.35_bitrate_4M.sh + +Explanation: +use it like: +usrp_rx_cfile[_basicrxcomplex_fpga].py -R daughterboard_side -d 16 -f freq -F usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf -g gain -N numberofsamplestoget data_cfloat.raw + +daughterboard_side should be A or B +f is the frequency in Hertz +gain is in decibels (use 10 for basicRX, use 30 for dbsRX) + +If you try to prerecord a stream which is send with the same usrp at the same time then +you must give the fpga firmware filename on the commandline with -F fpga_filename.rbf + +(Otherwise the usrp_rx_cfile_XXX_fpga.py script tries to load the + default firmware while the benchmark_tx_qpsk_fpga.py has loaded the + qpsk firmware, which will halt both scripts) + +Now you can demodulate the stream with usrp_rx_cfile_complex_fpga.py +The default filename of the prerecorded stream is data_cfloat.raw + +benchmark_rx_qpsk_file.py -m dqpsk -F data_cfloat.raw -f 0.0 -r 4000000 -v -S 2 -d 16 --excess-bw=0.35 + +./benchmark_rx_qpsk_file.py -h +usage: benchmark_rx_qpsk_file.py [options] + +options: + -h, --help show this help message and exit + -mMODULATION, --modulation=MODULATION + Select modulation from: qam64, d8psk, qam16, dbpsk, + dqpsk, gmsk [default=%default] + -FFILENAME, --filename=FILENAME + filename + -fFREQ, --freq=FREQ set Tx and/or Rx frequency to FREQ [default=%default] + -rBITRATE, --bitrate=BITRATE + specify bitrate. samples-per-symbol and interp/decim + will be derived. + -v, --verbose + + Expert: + -SSAMPLES_PER_SYMBOL, --samples-per-symbol=SAMPLES_PER_SYMBOL + set samples/symbol [default=%default] + --excess-bw=EXCESS_BW + set RRC excess bandwith factor [default=%default] (PSK) + + + + + Property changes on: README_USRP_QPSK_examples.txt ___________________________________________________________________ Name: svn:executable + * Index: README_USRP_QPSK.txt =================================================================== --- README_USRP_QPSK.txt (revision 0) +++ README_USRP_QPSK.txt (revision 0) @@ -0,0 +1,39 @@ +These are special fpga firmwares for the USRP to enable high-bitrate qpsk transmitting. +The firmware has a built-in RRCfilter, fractional interpolator and qpsk modulator. +It can be used with rfx and basic TX daughterboards. + +The easiest way to get going is: +unpack and install gnuradio-3.qpsk4.tar.gz: +tar zxvf gnuradio-3.qpsk4.tar.gz +cd gnuradio-3.qpsk4 +./configure +make +sudo make install + +Now gnuradio is installed and the special fpga firmware should be in /usr/local/share/usrp/rev2 and /usr/local/share/usrp/rev4 +to try it out: +cd gnuradio-examples/python/qpsk_fpga +tar zxvf commandline examples.tar.gz + +use commandline examples + +The examples are explained in gnuradio-examples/python/qpsk_fpga/README.txt + + +What is here: +README.txt this file +README_examples.txt explanation of example python scripts to test qpsk with special qpsk fpga firmware +gnuradio-3.qpsk4.tar.gz The source of the modified gnuradio distribution, includes special fpga firmware and qpsk_fpga examples +gnuradio-3.0svn_gnuradio3.qpsk4.diff diff between original gnuradio distribution and this one with special qpsk fpga firmware +usrp-3.qpsk4.tar.gz The source of the special usrp fpga firmware and driver (is subset of gnuradio-3.qpsk4.tar.gz) +usrp-3.0svn_usrp3.qpsk4.diff diff between original usrp sourcecode and this one with special qpsk fpga firmware + +qpsk_fpga_examples_4.tar.gz Examples on how to use the special qpsk fpga firmware using gnuradio + +The special qpsk fpga firmwares: (these should be in /usr/local/share/usrp/rev2 and /usr/local/share/usrp/rev4) +usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec10_DACint4X.rbf bitrate= 40Mbit/sec, alpha=0.2 +usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf bitrate= 4 Mbit/sec, alpha=0.2 +usrp_frac_interp_2rxhb_2tx_alpha0.35_int16_dec10_DACint4X.rbf bitrate= 40 Mbit/sec, alpha=0.35 +usrp_frac_interp_2rxhb_2tx_alpha0.35_int16_dec1_DACint4X.rbf bitrate= 4 Mbit/sec, alpha=0.35 + + Property changes on: README_USRP_QPSK.txt ___________________________________________________________________ Name: svn:executable + * Index: configure.ac =================================================================== --- configure.ac (revision 6827) +++ configure.ac (working copy) @@ -17,12 +17,13 @@ dnl the Free Software Foundation, Inc., 51 Franklin Street, dnl Boston, MA 02110-1301, USA. + AC_INIT AC_PREREQ(2.57) AM_CONFIG_HEADER(config.h) AC_CANONICAL_HOST AC_CANONICAL_TARGET([]) -AM_INIT_AUTOMAKE(gnuradio,3.0svn) +AM_INIT_AUTOMAKE(gnuradio,3.qpsk4) AC_CONFIG_SRCDIR([gnuradio-core/src/lib/runtime/gr_vmcircbuf.cc]) GR_X86_64 dnl check for lib64 suffix Index: README_USRP_QPSK_verilog_generator.txt =================================================================== --- README_USRP_QPSK_verilog_generator.txt (revision 0) +++ README_USRP_QPSK_verilog_generator.txt (revision 0) @@ -0,0 +1,81 @@ + +The verilog code for the fractional interpolating Root-Raised-Cosine filter is generated by a script. +usrp/fpga/sdr_lib/generate_frac_interp_05nov2007.py + +With this script you can generate code for any fractional interpolation factor and any alpha value (for the RRC) + +The symbolrate you get is 32*decimation/interpolation Mbit/sec +The bitrate you get for QPSK is 2*symbolrate +The bandwith you use is (1.0+alpha)*symbolrate + +decimation is 1 to 16 +interpolation is 1 to 16 + +To get instructions just call: + generate_frac_interp_05nov2007.py --help + +By generating your own code you can choose your needed bitrate and alpha value. + +There is also a script which generates all files needed to build the 4 rbfs which are already in this distribution. +usrp/fpga/sdr_lib/generate_all_frac_interp_files.sh +You can look in this script to see examples on how to use generate_frac_interp_05nov2007.py + +When you run it you get: + Generating code for fractional interpolating Root-Raised_Cosine filters in verilog for USRP + Generating verilog files for both I and Q channels for alpha 0.2 and 0.35 and for 4 Mbit and 40 Mbit + *int16_dec10*.v are for 40 Mbit QPSK and *int16_dec1*.v are for 4 Mbit QPSK + done + For bitrate=40 Mbit/sec and alpha=0.35 use the following two files + frac_interp_alpha0.35_int16_dec10_DACint4X_chan0.v + frac_interp_alpha0.35_int16_dec10_DACint4X_chan1.v + For bitrate=4 Mbit/sec and alpha=0.35 use the following two files + frac_interp_alpha0.35_int16_dec1_DACint4X_chan0.v + frac_interp_alpha0.35_int16_dec1_DACint4X_chan1.v + For bitrate=40 Mbit/sec and alpha=0.2 use the following two files + frac_interp_alpha0.2_int16_dec10_DACint4X_chan1.v + frac_interp_alpha0.2_int16_dec10_DACint4X_chan0.v + For bitrate=4 Mbit/sec and alpha=0.2 use the following two files + frac_interp_alpha0.2_int16_dec1_DACint4X_chan0.v + frac_interp_alpha0.2_int16_dec1_DACint4X_chan1.v + Copy the two files to usrp/fpga/sdr_lib/frac_interp_0.v and frac_interp_1.v + After copying the two files, build the rbf file with the Altera Quartus II software. + Make sure you use this special patched usrp sourcetree for usrp_qpsk. At the moment the standard usrp sourctree doesn't know about these files + Written by Martin Dudok van Heel, 2007 + Olifantasia + +With these files the following rbs are built: +usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec10_DACint4X.rbf bitrate= 40Mbit/sec, alpha=0.2 +usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf bitrate= 4 Mbit/sec, alpha=0.2 +usrp_frac_interp_2rxhb_2tx_alpha0.35_int16_dec10_DACint4X.rbf bitrate= 40 Mbit/sec, alpha=0.35 +usrp_frac_interp_2rxhb_2tx_alpha0.35_int16_dec1_DACint4X.rbf bitrate= 4 Mbit/sec, alpha=0.35 + + +usrp/fpga/sdr_lib/generate_frac_interp_05nov2007.py --help +usage: generate_frac_interp_05nov2007.py: [options] + +options: + -h, --help show this help message and exit + -c CHANNEL, --channel=CHANNEL + set which channel to generate (0 or 1) [default=0] + -n NTAPS_PER_FILTER, --ntaps-per-filter=NTAPS_PER_FILTER + set number of taps per interpolation phase + [default=11] + -d DECIMATION, --decimation=DECIMATION + set rrc decimation rate to DECIM [default=10] + -i INTERPOLATION, --interpolation=INTERPOLATION + set rrc decimation rate to INTERP [default=16] + -a ALPHA, --alpha=ALPHA + set rrc alpha to ALPHA (default=0.35.) (Common used + values are 0.15, 0.2 and 0.35) + -D DATA_SIZE, --data-size=DATA_SIZE + number of bits used for data per memory. (default=5) + (This has nothing to do with precision, but all with + the size of ramblocks in the fpga) + -P PHASE_SIZE, --phase-size=PHASE_SIZE + number of bits used for interpolation phases. + (default=4) (This has nothing to do with precision, + but all with the size of ramblocks in the fpga) + + +Written by Martin Dudok van Heel, 2007 +Olifantasia Index: gnuradio-examples/python/Makefile.am =================================================================== --- gnuradio-examples/python/Makefile.am (revision 6827) +++ gnuradio-examples/python/Makefile.am (working copy) @@ -20,4 +20,4 @@ # SUBDIRS = apps audio channel-coding digital_voice digital multi-antenna \ - multi_usrp networking usrp + multi_usrp networking usrp qpsk_fpga Index: gnuradio-examples/python/qpsk_fpga/commandline_tx_txA_rfx900_alpha_0.2_bitrate_4M_freq_900MHz.sh =================================================================== --- gnuradio-examples/python/qpsk_fpga/commandline_tx_txA_rfx900_alpha_0.2_bitrate_4M_freq_900MHz.sh (revision 0) +++ gnuradio-examples/python/qpsk_fpga/commandline_tx_txA_rfx900_alpha_0.2_bitrate_4M_freq_900MHz.sh (revision 0) @@ -0,0 +1,2 @@ +#!/bin/sh +./benchmark_tx_qpsk_fpga.py -T A -f 900.0e6 -v -F usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf -I 16 -D 1 Property changes on: gnuradio-examples/python/qpsk_fpga/commandline_tx_txA_rfx900_alpha_0.2_bitrate_4M_freq_900MHz.sh ___________________________________________________________________ Name: svn:executable + * Index: gnuradio-examples/python/qpsk_fpga/receive_path_qpsk_file.py =================================================================== --- gnuradio-examples/python/qpsk_fpga/receive_path_qpsk_file.py (revision 0) +++ gnuradio-examples/python/qpsk_fpga/receive_path_qpsk_file.py (revision 0) @@ -0,0 +1,256 @@ +#!/usr/bin/env python +# +# Copyright 2005,2006 Free Software Foundation, Inc. +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +from gnuradio import gr, gru, blks +from gnuradio import usrp +from gnuradio import eng_notation +import copy +import sys + +# from current dir +from pick_bitrate import pick_rx_bitrate + +# ///////////////////////////////////////////////////////////////////////////// +# receive path +# ///////////////////////////////////////////////////////////////////////////// + +class receive_path_qpsk_file(gr.hier_block): + def __init__(self, fg, demod_class, rx_callback, options): + + options = copy.copy(options) # make a copy so we can destructively modify + + self._verbose = options.verbose + self._rx_freq = options.rx_freq # receiver's center frequency + self._rx_gain = options.rx_gain # receiver's gain + self._rx_subdev_spec = options.rx_subdev_spec # daughterboard to use + self._bitrate = options.bitrate # desired bit rate + self._decim = options.decim # Decimating rate for the USRP (prelim) + self._samples_per_symbol = options.samples_per_symbol # desired samples/symbol + self._fusb_block_size = options.fusb_block_size # usb info for USRP + self._fusb_nblocks = options.fusb_nblocks # usb info for USRP + + self._rx_callback = rx_callback # this callback is fired when there's a packet available + self._demod_class = demod_class # the demodulator_class we're using + + if self._rx_freq is None: + sys.stderr.write("-f FREQ or --freq FREQ or --rx-freq FREQ must be specified\n") + raise SystemExit + + # Set up USRP source; also adjusts decim, samples_per_symbol, and bitrate + self._setup_file_source(options.filename) + + # copy the final answers back into options for use by demodulator + options.samples_per_symbol = self._samples_per_symbol + options.bitrate = self._bitrate + options.decim = self._decim + + # Get demod_kwargs + demod_kwargs = self._demod_class.extract_kwargs_from_options(options) + + # Design filter to get actual channel we want + sw_decim = 1 + chan_coeffs = gr.firdes.low_pass (1.0, # gain + sw_decim * self._samples_per_symbol, # sampling rate + 1.0, # midpoint of trans. band + 0.1, # width of trans. band + gr.firdes.WIN_HANN) # filter type + + # Decimating channel filter + # complex in and out, float taps + self.chan_filt = gr.fft_filter_ccc(sw_decim, chan_coeffs) + #self.chan_filt = gr.fir_filter_ccf(sw_decim, chan_coeffs) + + # receiver + self.packet_receiver = \ + blks.demod_pkts(fg, + self._demod_class(fg, **demod_kwargs), + access_code=None, + callback=self._rx_callback, + threshold=-1) + + #ok = self.set_freq(self._rx_freq) + #if not ok: + # print "Failed to set Rx frequency to %s" % (eng_notation.num_to_str(self._rx_freq)) + # raise ValueError, eng_notation.num_to_str(self._rx_freq) + + #g = self.subdev.gain_range() + #if options.show_rx_gain_range: + # print "Rx Gain Range: minimum = %g, maximum = %g, step size = %g" \ + # % (g[0], g[1], g[2]) + + #self.set_gain(options.rx_gain) + + #self.set_auto_tr(True) # enable Auto Transmit/Receive switching + + # Carrier Sensing Blocks + alpha = 0.001 + thresh = 30 # in dB, will have to adjust + self.probe = gr.probe_avg_mag_sqrd_c(thresh,alpha) + fg.connect(self.chan_filt, self.probe) + + # Display some information about the setup + if self._verbose: + self._print_verbage() + + fg.connect(self.src, self.chan_filt, self.packet_receiver) + gr.hier_block.__init__(self, fg, None, None) + + def _setup_file_source(self,filename): + self.src = gr.file_source(gr.sizeof_gr_complex, filename,False) + #self.u = usrp.source_c (fusb_block_size=self._fusb_block_size, + # fusb_nblocks=self._fusb_nblocks, fpga_filename="tx_qpsk14_4X.rbf") + adc_rate = 64.0e6#self.u.adc_rate() + + # derive values of bitrate, samples_per_symbol, and decim from desired info + (self._bitrate, self._samples_per_symbol, self._decim) = \ + pick_rx_bitrate(self._bitrate, self._demod_class.bits_per_symbol(), \ + self._samples_per_symbol, self._decim, adc_rate) + + #self.u.set_decim_rate(self._decim) + + # determine the daughterboard subdevice we're using + #if self._rx_subdev_spec is None: + # self._rx_subdev_spec = usrp.pick_rx_subdevice(self.u) + #self.subdev = usrp.selected_subdev(self.u, self._rx_subdev_spec) + + #self.u.set_mux(usrp.determine_rx_mux_value(self.u, self._rx_subdev_spec)) + + def set_freq(self, target_freq): + """ + Set the center frequency we're interested in. + + @param target_freq: frequency in Hz + @rypte: bool + + Tuning is a two step process. First we ask the front-end to + tune as close to the desired frequency as it can. Then we use + the result of that operation and our target_frequency to + determine the value for the digital up converter. + """ + #r = self.u.tune(0, self.subdev, target_freq) + #if r: + return True + + #return False + + def set_gain(self, gain): + """ + Sets the analog gain in the USRP + """ + self.gain = gain + return True + #if gain is None: + # r = self.subdev.gain_range() + # gain = (r[0] + r[1])/2 # set gain to midpoint + #self.gain = gain + #return self.subdev.set_gain(gain) + + def set_auto_tr(self, enable): + return True + #return self.subdev.set_auto_tr(enable) + + def bitrate(self): + return self._bitrate + + def samples_per_symbol(self): + return self._samples_per_symbol + + def decim(self): + return self._decim + + def carrier_sensed(self): + """ + Return True if we think carrier is present. + """ + #return self.probe.level() > X + return self.probe.unmuted() + + def carrier_threshold(self): + """ + Return current setting in dB. + """ + return self.probe.threshold() + + def set_carrier_threshold(self, threshold_in_db): + """ + Set carrier threshold. + + @param threshold_in_db: set detection threshold + @type threshold_in_db: float (dB) + """ + self.probe.set_threshold(threshold_in_db) + + + def add_options(normal, expert): + """ + Adds receiver-specific options to the Options Parser + """ + add_freq_option(normal) + if not normal.has_option("--bitrate"): + normal.add_option("-r", "--bitrate", type="eng_float", default=None, + help="specify bitrate. samples-per-symbol and interp/decim will be derived.") + normal.add_option("-R", "--rx-subdev-spec", type="subdev", default=None, + help="select USRP Rx side A or B") + normal.add_option("", "--rx-gain", type="eng_float", default=None, metavar="GAIN", + help="set receiver gain in dB [default=midpoint]. See also --show-rx-gain-range") + normal.add_option("", "--show-rx-gain-range", action="store_true", default=False, + help="print min and max Rx gain available on selected daughterboard") + normal.add_option("-v", "--verbose", action="store_true", default=False) + expert.add_option("-S", "--samples-per-symbol", type="int", default=None, + help="set samples/symbol [default=%default]") + expert.add_option("", "--rx-freq", type="eng_float", default=None, + help="set Rx frequency to FREQ [default=%default]", metavar="FREQ") + expert.add_option("-d", "--decim", type="intx", default=None, + help="set fpga decimation rate to DECIM [default=%default]") + expert.add_option("", "--log", action="store_true", default=False, + help="Log all parts of flow graph to files (CAUTION: lots of data)") + + # Make a static method to call before instantiation + add_options = staticmethod(add_options) + + + def _print_verbage(self): + """ + Prints information about the receive path + """ + #print "Using RX d'board %s" % (self.subdev.side_and_name(),) + #print "Rx gain: %g" % (self.gain,) + print "modulation: %s" % (self._demod_class.__name__) + print "bitrate: %sb/s" % (eng_notation.num_to_str(self._bitrate)) + print "samples/symbol: %3d" % (self._samples_per_symbol) + print "decim: %3d" % (self._decim) + #print "Rx Frequency: %s" % (eng_notation.num_to_str(self._rx_freq)) + # print "Rx Frequency: %f" % (self._rx_freq) + +def add_freq_option(parser): + """ + Hackery that has the -f / --freq option set both tx_freq and rx_freq + """ + def freq_callback(option, opt_str, value, parser): + parser.values.rx_freq = value + parser.values.tx_freq = value + + if not parser.has_option('--freq'): + parser.add_option('-f', '--freq', type="eng_float", + action="callback", callback=freq_callback, + help="set Tx and/or Rx frequency to FREQ [default=%default]", + metavar="FREQ") Index: gnuradio-examples/python/qpsk_fpga/commandline_rx_realtime_usrp0_rxB_dbsrx_alpha0.2_bitrate_4M_freq_900MHz.sh =================================================================== --- gnuradio-examples/python/qpsk_fpga/commandline_rx_realtime_usrp0_rxB_dbsrx_alpha0.2_bitrate_4M_freq_900MHz.sh (revision 0) +++ gnuradio-examples/python/qpsk_fpga/commandline_rx_realtime_usrp0_rxB_dbsrx_alpha0.2_bitrate_4M_freq_900MHz.sh (revision 0) @@ -0,0 +1,2 @@ +#!/bin/sh +./benchmark_rx_qpsk_fpga.py -m dqpsk -R B -f 900.0e6 -F usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf --excess-bw 0.2 -r 4000000 --rx-gain 30 -u 0 Index: gnuradio-examples/python/qpsk_fpga/commandline_tx_txA_basicTX_alpha_0.2_bitrate_40M_freq_16Mhz.sh =================================================================== --- gnuradio-examples/python/qpsk_fpga/commandline_tx_txA_basicTX_alpha_0.2_bitrate_40M_freq_16Mhz.sh (revision 0) +++ gnuradio-examples/python/qpsk_fpga/commandline_tx_txA_basicTX_alpha_0.2_bitrate_40M_freq_16Mhz.sh (revision 0) @@ -0,0 +1,2 @@ +#!/bin/sh +./benchmark_tx_qpsk_fpga.py -T A -f 16.0e6 -v -F usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec10_DACint4X.rbf -I 16 -D 10 Property changes on: gnuradio-examples/python/qpsk_fpga/commandline_tx_txA_basicTX_alpha_0.2_bitrate_40M_freq_16Mhz.sh ___________________________________________________________________ Name: svn:executable + * Index: gnuradio-examples/python/qpsk_fpga/commandline_rx_file_usrp0_rxA_basicRX_freq_16MHz_alpha_0.2_bitrate_4M.sh =================================================================== --- gnuradio-examples/python/qpsk_fpga/commandline_rx_file_usrp0_rxA_basicRX_freq_16MHz_alpha_0.2_bitrate_4M.sh (revision 0) +++ gnuradio-examples/python/qpsk_fpga/commandline_rx_file_usrp0_rxA_basicRX_freq_16MHz_alpha_0.2_bitrate_4M.sh (revision 0) @@ -0,0 +1,4 @@ +#!/bin/sh +./usrp_rx_cfile_basicrxcomplex_fpga.py -u 0 -R A -d 16 -f 16.0e6 -F usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf -g 10 -N 10000000 data_cfloat.raw +./benchmark_rx_qpsk_file.py -m dqpsk -d 16 -f 0 -S 2 -r 40000000 -v --excess-bw=0.2 + Property changes on: gnuradio-examples/python/qpsk_fpga/commandline_rx_file_usrp0_rxA_basicRX_freq_16MHz_alpha_0.2_bitrate_4M.sh ___________________________________________________________________ Name: svn:executable + * Index: gnuradio-examples/python/qpsk_fpga/commandline_tx_txA_rfx900_alpha_0.35_bitrate_40M_freq_900Mhz.sh =================================================================== --- gnuradio-examples/python/qpsk_fpga/commandline_tx_txA_rfx900_alpha_0.35_bitrate_40M_freq_900Mhz.sh (revision 0) +++ gnuradio-examples/python/qpsk_fpga/commandline_tx_txA_rfx900_alpha_0.35_bitrate_40M_freq_900Mhz.sh (revision 0) @@ -0,0 +1,2 @@ +#!/bin/sh +./benchmark_tx_qpsk_fpga.py -T A -f 900.0e6 -v -F usrp_frac_interp_2rxhb_2tx_alpha0.35_int16_dec10_DACint4X.rbf -I 16 -D 10 Property changes on: gnuradio-examples/python/qpsk_fpga/commandline_tx_txA_rfx900_alpha_0.35_bitrate_40M_freq_900Mhz.sh ___________________________________________________________________ Name: svn:executable + * Index: gnuradio-examples/python/qpsk_fpga/benchmark_rx_qpsk_file.py =================================================================== --- gnuradio-examples/python/qpsk_fpga/benchmark_rx_qpsk_file.py (revision 0) +++ gnuradio-examples/python/qpsk_fpga/benchmark_rx_qpsk_file.py (revision 0) @@ -0,0 +1,116 @@ +#!/usr/bin/env python +# +# Copyright 2005,2006 Free Software Foundation, Inc. +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +from gnuradio import gr, gru, modulation_utils +from gnuradio import usrp +from gnuradio import eng_notation +from gnuradio.eng_option import eng_option +from optparse import OptionParser + +import random +import struct +import sys + +# from current dir +#from receive_path import receive_path +from receive_path_qpsk_file import receive_path_qpsk_file +import fusb_options + +#import os +#print os.getpid() +#raw_input('Attach and press enter: ') + + +class my_graph(gr.flow_graph): + + def __init__(self, demod_class, rx_callback, options): + gr.flow_graph.__init__(self) + self.rxpath = receive_path_qpsk_file(self, demod_class, rx_callback, options) + +# ///////////////////////////////////////////////////////////////////////////// +# main +# ///////////////////////////////////////////////////////////////////////////// + +global n_rcvd, n_right + +def main(): + global n_rcvd, n_right + + n_rcvd = 0 + n_right = 0 + + def rx_callback(ok, payload): + global n_rcvd, n_right + (pktno,) = struct.unpack('!H', payload[0:2]) + n_rcvd += 1 + if ok: + n_right += 1 + + print "ok = %5s pktno = %4d n_rcvd = %4d n_right = %4d" % ( + ok, pktno, n_rcvd, n_right) + + + demods = modulation_utils.type_1_demods() + + # Create Options Parser: + parser = OptionParser (option_class=eng_option, conflict_handler="resolve") + expert_grp = parser.add_option_group("Expert") + + parser.add_option("-m", "--modulation", type="choice", choices=demods.keys(), + default='gmsk', + help="Select modulation from: %s [default=%%default]" + % (', '.join(demods.keys()),)) + parser.add_option("-F", "--filename", default="data_cfloat.raw", + help="filename") + receive_path_qpsk_file.add_options(parser, expert_grp) + + for mod in demods.values(): + mod.add_options(expert_grp) + + fusb_options.add_options(expert_grp) + (options, args) = parser.parse_args () + + if len(args) != 0: + parser.print_help(sys.stderr) + sys.exit(1) + + #if options.rx_freq is None: + # sys.stderr.write("You must specify -f FREQ or --freq FREQ\n") + # parser.print_help(sys.stderr) + # sys.exit(1) + + + # build the graph + fg = my_graph(demods[options.modulation], rx_callback, options) + + r = gr.enable_realtime_scheduling() + if r != gr.RT_OK: + print "Warning: Failed to enable realtime scheduling." + + fg.start() # start flow graph + fg.wait() # wait for it to finish + +if __name__ == '__main__': + try: + main() + except KeyboardInterrupt: + pass Index: gnuradio-examples/python/qpsk_fpga/pick_bitrate.py =================================================================== --- gnuradio-examples/python/qpsk_fpga/pick_bitrate.py (revision 0) +++ gnuradio-examples/python/qpsk_fpga/pick_bitrate.py (revision 0) @@ -0,0 +1,143 @@ +# +# Copyright 2005,2006 Free Software Foundation, Inc. +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +_default_bitrate = 500e3 + +_valid_samples_per_symbol = (2,3,4,5,6,7) + +def _gen_tx_info(converter_rate): + results = [] + for samples_per_symbol in _valid_samples_per_symbol: + for interp in range(16, 512 + 1, 4): + bitrate = converter_rate / interp / samples_per_symbol + results.append((bitrate, samples_per_symbol, interp)) + results.sort() + return results + +def _gen_rx_info(converter_rate): + results = [] + for samples_per_symbol in _valid_samples_per_symbol: + for decim in range(8, 256 + 1, 2): + bitrate = converter_rate / decim / samples_per_symbol + results.append((bitrate, samples_per_symbol, decim)) + results.sort() + return results + +def _filter_info(info, samples_per_symbol, xrate): + if samples_per_symbol is not None: + info = [x for x in info if x[1] == samples_per_symbol] + if xrate is not None: + info = [x for x in info if x[2] == xrate] + return info + +def _pick_best(target_bitrate, bits_per_symbol, info): + """ + @returns tuple (bitrate, samples_per_symbol, interp_rate_or_decim_rate) + """ + if len(info) == 0: + raise RuntimeError, "info is zero length!" + + if target_bitrate is None: # return the fastest one + return info[-1] + + # convert bit rate to symbol rate + target_symbolrate = target_bitrate / bits_per_symbol + + # Find the closest matching symbol rate. + # In the event of a tie, the one with the lowest samples_per_symbol wins. + # (We already sorted them, so the first one is the one we take) + + best = info[0] + best_delta = abs(target_symbolrate - best[0]) + for x in info[1:]: + delta = abs(target_symbolrate - x[0]) + if delta < best_delta: + best_delta = delta + best = x + + # convert symbol rate back to bit rate + return ((best[0] * bits_per_symbol),) + best[1:] + +def _pick_bitrate(bitrate, bits_per_symbol, samples_per_symbol, + xrate, converter_rate, gen_info): + """ + @returns tuple (bitrate, samples_per_symbol, interp_rate_or_decim_rate) + """ + if not isinstance(bits_per_symbol, int) or bits_per_symbol < 1: + raise ValueError, "bits_per_symbol must be an int >= 1" + + if samples_per_symbol is not None and xrate is not None: # completely determined + return (float(converter_rate) / xrate / samples_per_symbol, + samples_per_symbol, xrate) + + if bitrate is None and samples_per_symbol is None and xrate is None: + bitrate = _default_bitrate + + # now we have a target bitrate and possibly an xrate or + # samples_per_symbol constraint, but not both of them. + + return _pick_best(bitrate, bits_per_symbol, + _filter_info(gen_info(converter_rate), samples_per_symbol, xrate)) + +# --------------------------------------------------------------------------------------- + +def pick_tx_bitrate(bitrate, bits_per_symbol, samples_per_symbol, + interp_rate, converter_rate=128e6): + """ + Given the 4 input parameters, return at configuration that matches + + @param bitrate: desired bitrate or None + @type bitrate: number or None + @param bits_per_symbol: E.g., BPSK -> 1, QPSK -> 2, 8-PSK -> 3 + @type bits_per_symbol: integer >= 1 + @param samples_per_symbol: samples/baud (aka samples/symbol) + @type samples_per_symbol: number or None + @param interp_rate: USRP interpolation factor + @type interp_rate: integer or None + @param converter_rate: converter sample rate in Hz + @type converter_rate: number + + @returns tuple (bitrate, samples_per_symbol, interp_rate) + """ + return _pick_bitrate(bitrate, bits_per_symbol, samples_per_symbol, + interp_rate, converter_rate, _gen_tx_info) + + +def pick_rx_bitrate(bitrate, bits_per_symbol, samples_per_symbol, + decim_rate, converter_rate=64e6): + """ + Given the 4 input parameters, return at configuration that matches + + @param bitrate: desired bitrate or None + @type bitrate: number or None + @param bits_per_symbol: E.g., BPSK -> 1, QPSK -> 2, 8-PSK -> 3 + @type bits_per_symbol: integer >= 1 + @param samples_per_symbol: samples/baud (aka samples/symbol) + @type samples_per_symbol: number or None + @param decim_rate: USRP decimation factor + @type decim_rate: integer or None + @param converter_rate: converter sample rate in Hz + @type converter_rate: number + + @returns tuple (bitrate, samples_per_symbol, decim_rate) + """ + return _pick_bitrate(bitrate, bits_per_symbol, samples_per_symbol, + decim_rate, converter_rate, _gen_rx_info) Index: gnuradio-examples/python/qpsk_fpga/usrp_rx_cfile_fpga.py =================================================================== --- gnuradio-examples/python/qpsk_fpga/usrp_rx_cfile_fpga.py (revision 0) +++ gnuradio-examples/python/qpsk_fpga/usrp_rx_cfile_fpga.py (revision 0) @@ -0,0 +1,114 @@ +#!/usr/bin/env python + +""" +Read samples from the USRP and write to file formatted as binary +outputs single precision complex float values or complex short values (interleaved 16 bit signed short integers). + +""" + +from gnuradio import gr, eng_notation +from gnuradio import audio +from gnuradio import usrp +from gnuradio.eng_option import eng_option +from optparse import OptionParser + +class my_graph(gr.flow_graph): + + def __init__(self): + gr.flow_graph.__init__(self) + + usage="%prog: [options] output_filename" + parser = OptionParser(option_class=eng_option, usage=usage) + parser.add_option("-u", "--usrp", type="int", default=0, + help="which usrp to use (0, 1, 2 ...) [default=0]") + parser.add_option("-R", "--rx-subdev-spec", type="subdev", default=(0, 0), + help="select USRP Rx side A or B (default=A)") + parser.add_option("-d", "--decim", type="int", default=16, + help="set fgpa decimation rate to DECIM [default=%default]") + parser.add_option("-f", "--freq", type="eng_float", default=None, + help="set frequency to FREQ", metavar="FREQ") + parser.add_option("-F", "--fpga", default="std_2rxhb_2tx.rbf", + help="set fpga_filename to FPGA [default=%default]") + parser.add_option("-g", "--gain", type="eng_float", default=None, + help="set gain in dB (default is midpoint)") + parser.add_option("-8", "--width-8", action="store_true", default=False, + help="Enable 8-bit samples across USB") + parser.add_option( "--no-hb", action="store_true", default=False, + help="don't use halfband filter in usrp") + parser.add_option( "-s","--output-shorts", action="store_true", default=False, + help="output interleaved shorts in stead of complex floats") + parser.add_option("-N", "--nsamples", type="eng_float", default=None, + help="number of samples to collect [default=+inf]") + (options, args) = parser.parse_args () + if len(args) != 1: + parser.print_help() + raise SystemExit, 1 + filename = args[0] + + if options.freq is None: + parser.print_help() + sys.stderr.write('You must specify the frequency with -f FREQ\n'); + raise SystemExit, 1 + + # build the graph + if options.no_hb or (options.decim<8): + if options.fpga=="std_2rxhb_2tx.rbf": + self.fpga_filename="std_4rx_0tx.rbf" #Min decimation of this firmware is 4. contains 4 Rx paths without halfbands and 0 tx paths. + else: + self.fpga_filename=options.fpga + if options.output_shorts: + self.u = usrp.source_s(options.usrp,decim_rate=options.decim,fpga_filename=self.fpga_filename) + else: + self.u = usrp.source_c(options.usrp,decim_rate=options.decim,fpga_filename=self.fpga_filename) + else: + #standard fpga firmware "std_2rxhb_2tx.rbf" contains 2 Rx paths with halfband filters and 2 tx paths (the default) min decimation 8 + if options.output_shorts: + self.u = usrp.source_s(options.usrp,decim_rate=options.decim,fpga_filename=options.fpga) + else: + self.u = usrp.source_c(options.usrp,decim_rate=options.decim,fpga_filename=options.fpga) + if options.width_8: + sample_width = 8 + sample_shift = 8 + format = self.u.make_format(sample_width, sample_shift) + r = self.u.set_format(format) + if options.output_shorts: + self.dst = gr.file_sink(gr.sizeof_short, filename) + else: + self.dst = gr.file_sink(gr.sizeof_gr_complex, filename) + if options.nsamples is None: + self.connect(self.u, self.dst) + else: + if options.output_shorts: + self.head = gr.head(gr.sizeof_short, int(options.nsamples)*2) + else: + self.head = gr.head(gr.sizeof_gr_complex, int(options.nsamples)) + self.connect(self.u, self.head, self.dst) + + if options.rx_subdev_spec is None: + options.rx_subdev_spec = usrp.pick_rx_subdevice(self.u) + self.u.set_mux(usrp.determine_rx_mux_value(self.u, options.rx_subdev_spec)) + + # determine the daughterboard subdevice we're using + self.subdev = usrp.selected_subdev(self.u, options.rx_subdev_spec) + print "Using RX d'board %s" % (self.subdev.side_and_name(),) + input_rate = self.u.adc_freq() / self.u.decim_rate() + print "USB sample rate %s" % (eng_notation.num_to_str(input_rate)) + + if options.gain is None: + # if no gain was specified, use the mid-point in dB + g = self.subdev.gain_range() + options.gain = float(g[0]+g[1])/2 + + self.subdev.set_gain(options.gain) + + r = self.u.tune(0, self.subdev, options.freq) + if not r: + sys.stderr.write('Failed to set frequency\n') + raise SystemExit, 1 + + +if __name__ == '__main__': + try: + my_graph().run() + except KeyboardInterrupt: + pass Index: gnuradio-examples/python/qpsk_fpga/commandline_examples.tar.gz =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Property changes on: gnuradio-examples/python/qpsk_fpga/commandline_examples.tar.gz ___________________________________________________________________ Name: svn:mime-type + application/octet-stream Index: gnuradio-examples/python/qpsk_fpga/commandline_rx_realtime_usrp0_rxA_basicRX_alpha0.35_bitrate_4M_freq_16MHz.sh =================================================================== --- gnuradio-examples/python/qpsk_fpga/commandline_rx_realtime_usrp0_rxA_basicRX_alpha0.35_bitrate_4M_freq_16MHz.sh (revision 0) +++ gnuradio-examples/python/qpsk_fpga/commandline_rx_realtime_usrp0_rxA_basicRX_alpha0.35_bitrate_4M_freq_16MHz.sh (revision 0) @@ -0,0 +1,2 @@ +#!/bin/sh +./benchmark_rx_qpsk_fpga.py -m dqpsk -R A -f 16.0e6 -F usrp_frac_interp_2rxhb_2tx_alpha0.35_int16_dec1_DACint4X.rbf --excess-bw 0.35 -r 4000000 --rx-gain 10 -u 0 Property changes on: gnuradio-examples/python/qpsk_fpga/commandline_rx_realtime_usrp0_rxA_basicRX_alpha0.35_bitrate_4M_freq_16MHz.sh ___________________________________________________________________ Name: svn:executable + * Index: gnuradio-examples/python/qpsk_fpga/transmit_path_qpsk_fpga.py =================================================================== --- gnuradio-examples/python/qpsk_fpga/transmit_path_qpsk_fpga.py (revision 0) +++ gnuradio-examples/python/qpsk_fpga/transmit_path_qpsk_fpga.py (revision 0) @@ -0,0 +1,375 @@ +# +# Copyright 2005,2006 Free Software Foundation, Inc. +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +from gnuradio import gr, gru, blks +from gnuradio import usrp +from gnuradio import eng_notation + +import copy +import sys +import math + +from usrp_fpga_regs import * +# from current dir +from pick_bitrate import pick_tx_bitrate + +# ///////////////////////////////////////////////////////////////////////////// +# transmit path +# ///////////////////////////////////////////////////////////////////////////// + +class transmit_path_qpsk_fpga(gr.hier_block): + def __init__(self, fg, modulator_class, options): + ''' + See below for what options should hold + ''' + + options = copy.copy(options) # make a copy so we can destructively modify + + self._verbose = options.verbose + self._which_usrp = options.usrp # which usrp to use if you have multiple usrp plugged in. + # The last one plugged in is usrp 0, the one before is usrp 1. + self._tx_freq = options.tx_freq # tranmitter's center frequency + #self._tx_amplitude = options.tx_amplitude # digital amplitude sent to USRP + self._tx_subdev_spec = options.tx_subdev_spec # daughterboard to use + self._bitshift = options.bitshift #set the digital "attenuation" by shifting the output words to the right + #0 gives 0 dB, 1 gives 6 dB attenuation, 2 gives 12 dB, 3 gives 18 dB + #maximum is 15, realistic minimum is 0 + #You can actually use negative numbers up-untill -15 but anything below -1 most certainly gives huge distortion (don't use less then -1 unless you have really small fir coefficients in the fpga) + #especially for RFX boards you have to check the distortion + #1, 2 and 3 are good, gives >35 dB out-of-band suppression on RFX boards + #and >60 dB on basicTX + self._fpga = options.fpga #FPGA filename, determines interpolation_rate and excess-bw + self._dac_interp = options.dac_interp #DAC interpolation rate fixed in usrp driver, options are 2x and 4x, + #normally this is allways 4 + #make sure this is the same as in usrp driver + self._fi_interp = options.fi_interp #interpolation rate of fractional interpolator + #MAKE SURE THIS THE SAME AS IN SELECTED FPGA FIRMWARE + self._fi_decim = options.fi_decim #decimation rate of fractional interpolator in fpga + #MAKE SURE THIS THE SAME AS IN SELECTED FPGA FIRMWARE + self._interp_ratio = float(self._fi_interp)/float(self._fi_decim) #the interpolation ratio of the fractional interpolator (float) + self._interp_exact = self._interp_ratio*float(self._dac_interp) #the total exact interpolation rate (float) + self._interp =int(round(self._interp_exact)) #integer approximation of total interpolation rate + self._samples_per_symbol_exact=self._interp_exact #float + self._samples_per_symbol=int(round(self._samples_per_symbol_exact)) #integer approxiamtion of samples per symbol + + + self._bitrate_exact = -1.0 + self._bitrate = -1 # will be set by self._setup_usrp_sink() #options.bitrate # desired bit rate + + # desired samples/baud + self._fusb_block_size = options.fusb_block_size # usb info for USRP + self._fusb_nblocks = options.fusb_nblocks # usb info for USRP + + self._modulator_class = modulator_class # the modulator_class we are using + + if self._tx_freq is None: + sys.stderr.write("-f FREQ or --freq FREQ or --tx-freq FREQ must be specified\n") + raise SystemExit + + # Set up USRP sink; also adjusts interp, samples_per_symbol, and bitrate + self._setup_usrp_sink() + + # copy the final answers back into options for use by modulator + options.samples_per_symbol = self._samples_per_symbol + options.bitrate = self._bitrate + options.interp = self._interp + + # Get mod_kwargs + mod_kwargs = self._modulator_class.extract_kwargs_from_options(options) + + # Set center frequency of USRP + ok = self.set_freq(self._tx_freq) + if not ok: + print "Failed to set Tx frequency to %s" % (eng_notation.num_to_str(self._tx_freq),) + raise ValueError + + # transmitter + self.packet_transmitter = \ + blks.mod_pkts(fg, + self._modulator_class(fg, **mod_kwargs), + access_code=None, + msgq_limit=4, + pad_for_usrp=True) + + + # Set the USRP for maximum transmit gain + # (Note that on the RFX cards this is a nop.) + self.set_gain(self.subdev.gain_range()[0]) + + #self.amp = gr.multiply_const_cc(1) + #self.set_tx_amplitude(self._tx_amplitude) + + # enable Auto Transmit/Receive switching + self.set_auto_tr(True) + + # Display some information about the setup + if self._verbose: + self._print_verbage() + + # Create and setup transmit path flow graph + fg.connect(self.packet_transmitter, self.u) + gr.hier_block.__init__(self, fg, None, None) + + def _setup_usrp_sink(self): + """ + Creates a USRP sink, determines the settings for best bitrate, + and attaches to the transmitter's subdevice. + """ + self.u = usrp.sink_s(self._which_usrp,fusb_block_size=self._fusb_block_size, + fusb_nblocks=self._fusb_nblocks, + fpga_filename=self._fpga) + #fpga_filename="usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf") + #fpga_filename="usrp_0.2_16_14bit.rbf") + #fpga_filename="usrp_0.2_16_varbit3.rbf") + #usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec10_DACint4X.rbf") + #usrp_0.35_dec1_edited.rbf") + #usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec10_DACint4X.rbf") #fpga_filename="usrp_frac_interp_2rxhb_2tx_alpha0.35_int16_dec1_DACint4X.rbf") + #"tx_qpsk14_4X.rbf") + + #FR_USER_1 is register 65, reserved for user application. + #On the fractional interpolation fpga firmware this register is used to determine how many bits to shift the 18 bit output of the fractional interpolator to the left/right before it goes to the 14 bit DAC + self.u._u._write_fpga_reg (FR_USER_1, self._bitshift) #set the digital "attenuation" by shifting the output words to the right + #0 gives 0 dB, 1 gives 6 dB attenuation, 2 gives 12 dB, 3 gives 18 dB + #maximum is 15, realistic minimum is 0 + #You can actually use negative numbers up-untill -15 but anything below -1 most certainly gives huge distortion (don't use less then -1 unless you have really small fir coefficients in the fpga) + #realistic for reducing distortion are 0 to 4 + #especially for RFX boards you have to check the distortion + + + + dac_rate = self.u.dac_rate(); + + # derive values of bitrate, samples_per_symbol, and interp from desired info + #(self._bitrate, self._samples_per_symbol, self._interp) = \ + # pick_tx_bitrate(self._bitrate, self._modulator_class.bits_per_symbol(), + # self._samples_per_symbol, self._interp, dac_rate) + self._bitrate_exact=self._modulator_class.bits_per_symbol()*dac_rate/self._interp_exact + self._bitrate=round(self._bitrate_exact) + #When using usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec10_DACint4X.rbf + # self._bitrate should be 40 Mbit/sec + #When using usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf + # self._bitrate should be 4 Mbit/sec + max_usrp_int=512 + number_of_symbols_per_usrp_input_word=16 #usrp gets 16 bit input words (for both I and Q) which are split into 16 individual bits + wanted_usrp_int=int(self._interp/4)*4*number_of_symbols_per_usrp_input_word #only needed for usb throughput optimalisation + if wanted_usrp_int>max_usrp_int: + wanted_usrp_int=max_usrp_int + #print "wanted usrp driver int",wanted_usrp_int + self.u.set_interp_rate(wanted_usrp_int)#data is send and processed in blocks of 16 bits #/(16*4)) + #print "usrp driver interp",self.u.interp_rate() + + # determine the daughterboard subdevice we're using + if self._tx_subdev_spec is None: + self._tx_subdev_spec = usrp.pick_tx_subdevice(self.u) + self.u.set_mux(usrp.determine_tx_mux_value(self.u, self._tx_subdev_spec)) + self.subdev = usrp.selected_subdev(self.u, self._tx_subdev_spec) + + def tune_special(self,u, chan, subdev, target_freq): + """ + Set the center frequency we're interested in. + + @param u: instance of usrp.source_* or usrp.sink_* + @param chan: DDC/DUC channel + @type chan: int + @param subdev: daughterboard subdevice + @param target_freq: frequency in Hz + @returns False if failure else tune_result + + Tuning is a two step process. First we ask the front-end to + tune as close to the desired frequency as it can. Then we use + the result of that operation and our target_frequency to + determine the value for the digital down converter. + """ + + # Does this usrp instance do Tx or Rx? + rx_p = True + try: + u.rx_freq + except AttributeError: + rx_p = False + + ok, baseband_freq = subdev.set_freq(target_freq-24.0e6) + dxc_freq, inverted = usrp.calc_dxc_freq(target_freq, baseband_freq, u.converter_rate()) + + # If the spectrum is inverted, and the daughterboard doesn't do + # quadrature downconversion, we can fix the inversion by flipping the + # sign of the dxc_freq... (This only happens using the basic_rx board) + + if subdev.spectrum_inverted(): + inverted = not(inverted) + + if inverted and not(subdev.is_quadrature()): + dxc_freq = -dxc_freq + inverted = not(inverted) + + if rx_p: + ok = ok and u.set_rx_freq(chan, dxc_freq) + else: + dxc_freq = -dxc_freq + ok = ok and u.set_tx_freq(chan, dxc_freq) + + if not(ok): + return False + + # residual_freq is the offset left over because of dxc tuning step size + if rx_p: + residual_freq = dxc_freq - u.rx_freq(chan) + else: + # FIXME 50-50 chance this has the wrong sign... + residual_freq = dxc_freq - u.tx_freq(chan) + + return usrp.tune_result(baseband_freq, dxc_freq, residual_freq, inverted) + + def set_freq(self, target_freq): + """ + Set the center frequency we're interested in. + + @param target_freq: frequency in Hz + @rypte: bool + + Tuning is a two step process. First we ask the front-end to + tune as close to the desired frequency as it can. Then we use + the result of that operation and our target_frequency to + determine the value for the digital up converter. + """ + r = self.u.tune(self.subdev._which, self.subdev, target_freq) + #r = self.tune_special(self.u,self.subdev._which, self.subdev, target_freq) + if r: + print "baseband_freq=",r.baseband_freq + print "dxc_freq=",r.dxc_freq + print "residual_freq=",r.residual_freq + print "inverted=",r.inverted + return True + + return False + + def set_gain(self, gain): + """ + Sets the analog gain in the USRP + """ + self.gain = gain + self.subdev.set_gain(gain) + + #def set_tx_amplitude(self, ampl): + # """ + # Sets the transmit amplitude sent to the USRP + # @param: ampl 0 <= ampl < 32768. Try 8000 + # """ + # self._tx_amplitude = max(0.0, min(ampl, 32767.0)) + # self.amp.set_k(self._tx_amplitude) + + def set_auto_tr(self, enable): + """ + Turns on auto transmit/receive of USRP daughterboard (if exits; else ignored) + """ + return self.subdev.set_auto_tr(enable) + + def send_pkt(self, payload='', eof=False): + """ + Calls the transmitter method to send a packet + """ + return self.packet_transmitter.send_pkt(payload, eof) + + def bitrate(self): + return self._bitrate + + def samples_per_symbol(self): + return self._samples_per_symbol + + def interp(self): + return self._interp + + def add_options(normal, expert): + """ + Adds transmitter-specific options to the Options Parser + """ + add_freq_option(normal) + # bitrate is fixed at 40 Mbit/sec for qpsk and 20 Mbit/sec for bpsk + #if not normal.has_option('--bitrate'): + # normal.add_option("-r", "--bitrate", type="eng_float", default=None, + # help="specify bitrate. samples-per-symbol and interp/decim will be derived.") + normal.add_option("-u", "--usrp", type="int", default=0, + help="which usrp to use (0, 1, 2 ...) [default=0 is the last one plugged in]") + normal.add_option("-F", "--fpga", default="usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf", + help="set fpga_filename to FPGA [default=usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf]") + #std_2rxhb_2tx.rbf + #usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf 40 Mbit/sec alpha=0.2 + #usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec10_DACint4X.rbf 4 Mbit/sec alpha=0.2 + #usrp_frac_interp_2rxhb_2tx_alpha0.35_int16_dec1_DACint4X.rbf 40 Mbit/sec alpha=0.35 + #usrp_frac_interp_2rxhb_2tx_alpha0.35_int16_dec10_DACint4X.rbf 4 Mbit/sec alpha=0.35 + normal.add_option("-b", "--bitshift", type="int", default=2, + help="bitshift range(-15,15) determines the tx amplitude attenuation, higher values give more attenuation, a too low value gives overflows and/or distortion in RFX boards 0=> +6dB 1=>0 dB (tx_amplitude=8192) 1=>-6 dB (tx_amplitude=4096), 2=> -12 dB and so on. Values 1, 2 and 3 are good for RFX boards [default=2]") + normal.add_option ("-I", "--fi-interp", type="int", default=16, + help="give interpolation of fractional interpolator which is hardcoded in selected fgpa (only used to optimise usb transfers and calculate bitrate) [default=16]") + normal.add_option ("-D", "--fi-decim", type="int", default=1, + help="give decimation of fractional interpolator which is hardcoded in selected fgpa (only used to optimise usb transfers and calculate bitrate) [default=1]") + normal.add_option ("--dac-interp", type="int", default=4, + help="give interpolation of DAC (2 or 4) which is hardcoded in usrp driver (only used to optimise usb transfers and calculate bitrate) [default=4 which is currently the only valid option]") + normal.add_option("-T", "--tx-subdev-spec", type="subdev", default=None, + help="select USRP Tx side A or B") + #normal.add_option("", "--tx-amplitude", type="eng_float", default=12000, metavar="AMPL", + # help="set transmitter digital amplitude: 0 <= AMPL < 32768 [default=%default]") + normal.add_option("-v", "--verbose", action="store_true", default=False) + #samples-per-symbol is fixed in fpga firmware + #expert.add_option("-S", "--samples-per-symbol", type="int", default=None, + # help="set samples/symbol [default=%default]") + expert.add_option("", "--tx-freq", type="eng_float", default=None, + help="set transmit frequency to FREQ [default=%default]", metavar="FREQ") + #interp is fixed in fpga firmare + #expert.add_option("-i", "--interp", type="intx", default=None, + # help="set fpga interpolation rate to INTERP [default=%default]") + expert.add_option("", "--log", action="store_true", default=False, + help="Log all parts of flow graph to file (CAUTION: lots of data)") + + # Make a static method to call before instantiation + add_options = staticmethod(add_options) + + def _print_verbage(self): + """ + Prints information about the transmit path + """ + print "Using TX d'board %s" % (self.subdev.side_and_name(),) + print "FPGA filename %s" % (self._fpga) + print "Tx attenuation %f dB" % (-20*math.log10(2)*(self._bitshift-1)) + print "Tx digital amplitude %s" % ( 1<<(14-1-self._bitshift+1)) + print "modulation: %s" % (self._modulator_class.__name__) + print "bitrate exact: %f" % (self._bitrate_exact) + print "bitrate rounded: %sb/s" % (eng_notation.num_to_str(self._bitrate)) + print "samples/symbol exact: %f" % (self._samples_per_symbol_exact) + print "samples/symbol rounded: %3d" % (self._samples_per_symbol) + print "interp exact: %f" % (self._interp_exact) + print "interp rounded: %3d" % (self._interp) + print "Tx Frequency: %s" % (eng_notation.num_to_str(self._tx_freq)) + + +def add_freq_option(parser): + """ + Hackery that has the -f / --freq option set both tx_freq and rx_freq + """ + def freq_callback(option, opt_str, value, parser): + parser.values.rx_freq = value + parser.values.tx_freq = value + + if not parser.has_option('--freq'): + parser.add_option('-f', '--freq', type="eng_float", + action="callback", callback=freq_callback, + help="set Tx and/or Rx frequency to FREQ [default=%default]", + metavar="FREQ") Index: gnuradio-examples/python/qpsk_fpga/commandline_tx_txA_rfx900_alpha_0.2_bitrate_40M_freq_900MHz.sh =================================================================== --- gnuradio-examples/python/qpsk_fpga/commandline_tx_txA_rfx900_alpha_0.2_bitrate_40M_freq_900MHz.sh (revision 0) +++ gnuradio-examples/python/qpsk_fpga/commandline_tx_txA_rfx900_alpha_0.2_bitrate_40M_freq_900MHz.sh (revision 0) @@ -0,0 +1,2 @@ +#!/bin/sh +./benchmark_tx_qpsk_fpga.py -T A -f 900.0e6 -v -F usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec10_DACint4X.rbf -I 16 -D 10 Property changes on: gnuradio-examples/python/qpsk_fpga/commandline_tx_txA_rfx900_alpha_0.2_bitrate_40M_freq_900MHz.sh ___________________________________________________________________ Name: svn:executable + * Index: gnuradio-examples/python/qpsk_fpga/commandline_rx_file_usrp1_rxB_rfx900_freq_900MHz_alpha_0.2_bitrate_4M.sh =================================================================== --- gnuradio-examples/python/qpsk_fpga/commandline_rx_file_usrp1_rxB_rfx900_freq_900MHz_alpha_0.2_bitrate_4M.sh (revision 0) +++ gnuradio-examples/python/qpsk_fpga/commandline_rx_file_usrp1_rxB_rfx900_freq_900MHz_alpha_0.2_bitrate_4M.sh (revision 0) @@ -0,0 +1,4 @@ +#!/bin/sh +./usrp_rx_cfile_fpga.py -u 1 -R B -d 16 -f 900.0e6 -F usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf -g 30 -N 10000000 data_cfloat.raw +./benchmark_rx_qpsk_file.py -m dqpsk -d 16 -f 0 -S 2 -r 40000000 -v --excess-bw=0.2 + Property changes on: gnuradio-examples/python/qpsk_fpga/commandline_rx_file_usrp1_rxB_rfx900_freq_900MHz_alpha_0.2_bitrate_4M.sh ___________________________________________________________________ Name: svn:executable + * Index: gnuradio-examples/python/qpsk_fpga/commandline_rx_realtime_usrp0_rxA_basicRX_alpha0.2_bitrate_4M_freq_16MHz.sh =================================================================== --- gnuradio-examples/python/qpsk_fpga/commandline_rx_realtime_usrp0_rxA_basicRX_alpha0.2_bitrate_4M_freq_16MHz.sh (revision 0) +++ gnuradio-examples/python/qpsk_fpga/commandline_rx_realtime_usrp0_rxA_basicRX_alpha0.2_bitrate_4M_freq_16MHz.sh (revision 0) @@ -0,0 +1,2 @@ +#!/bin/sh +./benchmark_rx_qpsk_fpga.py -m dqpsk -R A -f 16.0e6 -F usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf --excess-bw 0.2 -r 4000000 --rx-gain 10 -u 0 Property changes on: gnuradio-examples/python/qpsk_fpga/commandline_rx_realtime_usrp0_rxA_basicRX_alpha0.2_bitrate_4M_freq_16MHz.sh ___________________________________________________________________ Name: svn:executable + * Index: gnuradio-examples/python/qpsk_fpga/commandline_tx_txA_basicTX_alpha_0.2_bitrate_40M_freq_0Hz.sh =================================================================== --- gnuradio-examples/python/qpsk_fpga/commandline_tx_txA_basicTX_alpha_0.2_bitrate_40M_freq_0Hz.sh (revision 0) +++ gnuradio-examples/python/qpsk_fpga/commandline_tx_txA_basicTX_alpha_0.2_bitrate_40M_freq_0Hz.sh (revision 0) @@ -0,0 +1,2 @@ +#!/bin/sh +./benchmark_tx_qpsk_fpga.py -T A -f 0.0e6 -v -F usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec10_DACint4X.rbf -I 16 -D 10 Property changes on: gnuradio-examples/python/qpsk_fpga/commandline_tx_txA_basicTX_alpha_0.2_bitrate_40M_freq_0Hz.sh ___________________________________________________________________ Name: svn:executable + * Index: gnuradio-examples/python/qpsk_fpga/receive_path_qpsk_fpga.py =================================================================== --- gnuradio-examples/python/qpsk_fpga/receive_path_qpsk_fpga.py (revision 0) +++ gnuradio-examples/python/qpsk_fpga/receive_path_qpsk_fpga.py (revision 0) @@ -0,0 +1,272 @@ +#!/usr/bin/env python +# +# Copyright 2005,2006 Free Software Foundation, Inc. +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +from gnuradio import gr, gru, blks +from gnuradio import usrp +from gnuradio import eng_notation +import copy +import sys + +# from current dir +from pick_bitrate import pick_rx_bitrate + +# ///////////////////////////////////////////////////////////////////////////// +# receive path +# ///////////////////////////////////////////////////////////////////////////// + +class receive_path_qpsk_fpga(gr.hier_block): + def __init__(self, fg, demod_class, rx_callback, options): + + options = copy.copy(options) # make a copy so we can destructively modify + + self._verbose = options.verbose + self._which_usrp = options.usrp # which usrp to use if you have multiple usrp plugged in. + # The last one plugged in is usrp 0, the one before is usrp 1. + self._fpga = options.fpga # which fpga filename to use + # If using both transmit and receive scripts at the same time on one usrp, + # fpga filename MUST be the same for both. + self._rx_freq = options.rx_freq # receiver's center frequency + self._rx_gain = options.rx_gain # receiver's gain + self._rx_subdev_spec = options.rx_subdev_spec # daughterboard to use + self._bitrate = options.bitrate # desired bit rate + self._decim = options.decim # Decimating rate for the USRP (prelim) + self._samples_per_symbol = options.samples_per_symbol # desired samples/symbol + self._fusb_block_size = options.fusb_block_size # usb info for USRP + self._fusb_nblocks = options.fusb_nblocks # usb info for USRP + + self._rx_callback = rx_callback # this callback is fired when there's a packet available + self._demod_class = demod_class # the demodulator_class we're using + + if self._rx_freq is None: + sys.stderr.write("-f FREQ or --freq FREQ or --rx-freq FREQ must be specified\n") + raise SystemExit + + # Set up USRP source; also adjusts decim, samples_per_symbol, and bitrate + self._setup_usrp_source() + + # copy the final answers back into options for use by demodulator + options.samples_per_symbol = self._samples_per_symbol + options.bitrate = self._bitrate + options.decim = self._decim + + # Get demod_kwargs + demod_kwargs = self._demod_class.extract_kwargs_from_options(options) + + # Design filter to get actual channel we want + sw_decim = 1 + chan_coeffs = gr.firdes.low_pass (1.0, # gain + sw_decim * self._samples_per_symbol, # sampling rate + 1.0, # midpoint of trans. band + 0.1, # width of trans. band + gr.firdes.WIN_HANN) # filter type + + # Decimating channel filter + # complex in and out, float taps + self.chan_filt = gr.fft_filter_ccc(sw_decim, chan_coeffs) + #self.chan_filt = gr.fir_filter_ccf(sw_decim, chan_coeffs) + + # receiver + self.packet_receiver = \ + blks.demod_pkts(fg, + self._demod_class(fg, **demod_kwargs), + access_code=None, + callback=self._rx_callback, + threshold=-1) + + ok = self.set_freq(self._rx_freq) + if not ok: + print "Failed to set Rx frequency to %s" % (eng_notation.num_to_str(self._rx_freq)) + raise ValueError, eng_notation.num_to_str(self._rx_freq) + + g = self.subdev.gain_range() + if options.show_rx_gain_range: + print "Rx Gain Range: minimum = %g, maximum = %g, step size = %g" \ + % (g[0], g[1], g[2]) + + self.set_gain(options.rx_gain) + + self.set_auto_tr(True) # enable Auto Transmit/Receive switching + + # Carrier Sensing Blocks + alpha = 0.001 + thresh = 30 # in dB, will have to adjust + self.probe = gr.probe_avg_mag_sqrd_c(thresh,alpha) + fg.connect(self.chan_filt, self.probe) + + # Display some information about the setup + if self._verbose: + self._print_verbage() + + fg.connect(self.u, self.chan_filt, self.packet_receiver) + gr.hier_block.__init__(self, fg, None, None) + + def _setup_usrp_source(self): + self.u = usrp.source_c (self._which_usrp,fusb_block_size=self._fusb_block_size, + fusb_nblocks=self._fusb_nblocks, + fpga_filename=self._fpga) + #fpga_filename="usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf") + #fpga_filename="usrp_frac_interp_2rxhb_2tx_alpha0.35_int16_dec1_DACint4X.rbf") + adc_rate = self.u.adc_rate() + + # derive values of bitrate, samples_per_symbol, and decim from desired info + (self._bitrate, self._samples_per_symbol, self._decim) = \ + pick_rx_bitrate(self._bitrate, self._demod_class.bits_per_symbol(), \ + self._samples_per_symbol, self._decim, adc_rate) + + self.u.set_decim_rate(self._decim) + print "self._decim",self._decim + + # determine the daughterboard subdevice we're using + if self._rx_subdev_spec is None: + self._rx_subdev_spec = usrp.pick_rx_subdevice(self.u) + self.subdev = usrp.selected_subdev(self.u, self._rx_subdev_spec) + + self.u.set_mux(usrp.determine_rx_mux_value(self.u, self._rx_subdev_spec)) + + def set_freq(self, target_freq): + """ + Set the center frequency we're interested in. + + @param target_freq: frequency in Hz + @rypte: bool + + Tuning is a two step process. First we ask the front-end to + tune as close to the desired frequency as it can. Then we use + the result of that operation and our target_frequency to + determine the value for the digital up converter. + """ + r = self.u.tune(0, self.subdev, target_freq) + if r: + return True + + return False + + def set_gain(self, gain): + """ + Sets the analog gain in the USRP + """ + if gain is None: + r = self.subdev.gain_range() + gain = (r[0] + r[1])/2 # set gain to midpoint + self.gain = gain + return self.subdev.set_gain(gain) + + def set_auto_tr(self, enable): + return self.subdev.set_auto_tr(enable) + + def bitrate(self): + return self._bitrate + + def samples_per_symbol(self): + return self._samples_per_symbol + + def decim(self): + return self._decim + + def carrier_sensed(self): + """ + Return True if we think carrier is present. + """ + #return self.probe.level() > X + return self.probe.unmuted() + + def carrier_threshold(self): + """ + Return current setting in dB. + """ + return self.probe.threshold() + + def set_carrier_threshold(self, threshold_in_db): + """ + Set carrier threshold. + + @param threshold_in_db: set detection threshold + @type threshold_in_db: float (dB) + """ + self.probe.set_threshold(threshold_in_db) + + + def add_options(normal, expert): + """ + Adds receiver-specific options to the Options Parser + """ + add_freq_option(normal) + if not normal.has_option("--bitrate"): + normal.add_option("-r", "--bitrate", type="eng_float", default=None, + help="specify bitrate. samples-per-symbol and interp/decim will be derived.") + normal.add_option("-u", "--usrp", type="int", default=0, + help="which usrp to use (0, 1, 2 ...) [default=0 is the last one plugged in]") + #normal.add_option("-F", "--fpga", default="std_2rxhb_2tx.rbf", + # help="set fpga_filename to FPGA [default=%default]") + normal.add_option("-F", "--fpga", default="usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf", + help="set fpga_filename to FPGA [default=usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf]") + #std_2rxhb_2tx.rbf + #usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf won't work datarate too high for usrp receive throughput + #usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec10_DACint4X.rbf + #usrp_frac_interp_2rxhb_2tx_alpha0.35_int16_dec1_DACint4X.rbf won't work datarate too high for usrp receive throughput + #usrp_frac_interp_2rxhb_2tx_alpha0.35_int16_dec10_DACint4X.rbf + normal.add_option("-R", "--rx-subdev-spec", type="subdev", default=None, + help="select USRP Rx side A or B") + normal.add_option("", "--rx-gain", type="eng_float", default=None, metavar="GAIN", + help="set receiver gain in dB [default=midpoint]. See also --show-rx-gain-range") + normal.add_option("", "--show-rx-gain-range", action="store_true", default=False, + help="print min and max Rx gain available on selected daughterboard") + normal.add_option("-v", "--verbose", action="store_true", default=False) + expert.add_option("-S", "--samples-per-symbol", type="int", default=None, + help="set samples/symbol [default=%default]") + expert.add_option("", "--rx-freq", type="eng_float", default=None, + help="set Rx frequency to FREQ [default=%default]", metavar="FREQ") + expert.add_option("-d", "--decim", type="intx", default=None, + help="set fpga decimation rate to DECIM [default=%default]") + expert.add_option("", "--log", action="store_true", default=False, + help="Log all parts of flow graph to files (CAUTION: lots of data)") + + # Make a static method to call before instantiation + add_options = staticmethod(add_options) + + + def _print_verbage(self): + """ + Prints information about the receive path + """ + print "Using RX d'board %s" % (self.subdev.side_and_name(),) + print "Rx gain: %g" % (self.gain,) + print "modulation: %s" % (self._demod_class.__name__) + print "bitrate: %sb/s" % (eng_notation.num_to_str(self._bitrate)) + print "samples/symbol: %3d" % (self._samples_per_symbol) + print "decim: %3d" % (self._decim) + print "Rx Frequency: %s" % (eng_notation.num_to_str(self._rx_freq)) + # print "Rx Frequency: %f" % (self._rx_freq) + +def add_freq_option(parser): + """ + Hackery that has the -f / --freq option set both tx_freq and rx_freq + """ + def freq_callback(option, opt_str, value, parser): + parser.values.rx_freq = value + parser.values.tx_freq = value + + if not parser.has_option('--freq'): + parser.add_option('-f', '--freq', type="eng_float", + action="callback", callback=freq_callback, + help="set Tx and/or Rx frequency to FREQ [default=%default]", + metavar="FREQ") Index: gnuradio-examples/python/qpsk_fpga/dqpsk_local.py =================================================================== --- gnuradio-examples/python/qpsk_fpga/dqpsk_local.py (revision 0) +++ gnuradio-examples/python/qpsk_fpga/dqpsk_local.py (revision 0) @@ -0,0 +1,374 @@ +# +# Copyright 2005,2006 Free Software Foundation, Inc. +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +# See gnuradio-examples/python/gmsk2 for examples + +""" +differential QPSK modulation and demodulation. +""" + +from gnuradio import gr, gru, modulation_utils +from math import pi, sqrt +import psk +import cmath +import Numeric +from pprint import pprint + +# default values (used in __init__ and add_options) +_def_samples_per_symbol = 2 +_def_excess_bw = 0.35 +_def_gray_code = True +_def_verbose = False +_def_log = False + +_def_costas_alpha = None +_def_gain_mu = 0.03 +_def_mu = 0.05 +_def_omega_relative_limit = 0.005 + + +# ///////////////////////////////////////////////////////////////////////////// +# DQPSK modulator +# ///////////////////////////////////////////////////////////////////////////// + +class dqpsk_mod(gr.hier_block): + + def __init__(self, fg, + samples_per_symbol=_def_samples_per_symbol, + excess_bw=_def_excess_bw, + gray_code=_def_gray_code, + verbose=_def_verbose, + log=_def_log): + """ + Hierarchical block for RRC-filtered QPSK modulation. + + The input is a byte stream (unsigned char) and the + output is the complex modulated signal at baseband. + + @param fg: flow graph + @type fg: flow graph + @param samples_per_symbol: samples per symbol >= 2 + @type samples_per_symbol: integer + @param excess_bw: Root-raised cosine filter excess bandwidth + @type excess_bw: float + @param gray_code: Tell modulator to Gray code the bits + @type gray_code: bool + @param verbose: Print information about modulator? + @type verbose: bool + @param debug: Print modualtion data to files? + @type debug: bool + """ + + self._fg = fg + self._samples_per_symbol = samples_per_symbol + self._excess_bw = excess_bw + self._gray_code = gray_code + + if not isinstance(samples_per_symbol, int) or samples_per_symbol < 2: + raise TypeError, ("sbp must be an integer >= 2, is %d" % samples_per_symbol) + + ntaps = 11 * samples_per_symbol + + arity = pow(2,self.bits_per_symbol()) + + # turn bytes into k-bit vectors + self.bytes2chunks = \ + gr.packed_to_unpacked_bb(self.bits_per_symbol(), gr.GR_MSB_FIRST) + + if self._gray_code: + self.symbol_mapper = gr.map_bb(psk.binary_to_gray[arity]) + else: + self.symbol_mapper = gr.map_bb(psk.binary_to_ungray[arity]) + + self.diffenc = gr.diff_encoder_bb(arity) + + rot = .707 + .707j + rotated_const = map(lambda pt: pt * rot, psk.constellation[arity]) + self.chunks2symbols = gr.chunks_to_symbols_bc(rotated_const) + + # pulse shaping filter + self.rrc_taps = gr.firdes.root_raised_cosine( + self._samples_per_symbol, # gain (sps since we're interpolating by sps) + self._samples_per_symbol, # sampling rate + 1.0, # symbol rate + self._excess_bw, # excess bandwidth (roll-off factor) + ntaps) + + self.rrc_filter = gr.interp_fir_filter_ccf(self._samples_per_symbol, self.rrc_taps) + + if verbose: + self._print_verbage() + + if log: + self._setup_logging() + + # Connect & Initialize base class + self._fg.connect(self.bytes2chunks, self.symbol_mapper, self.diffenc, + self.chunks2symbols, self.rrc_filter) + gr.hier_block.__init__(self, self._fg, self.bytes2chunks, self.rrc_filter) + + def samples_per_symbol(self): + return self._samples_per_symbol + + def bits_per_symbol(self=None): # staticmethod that's also callable on an instance + return 2 + bits_per_symbol = staticmethod(bits_per_symbol) # make it a static method. RTFM + + def _print_verbage(self): + print "bits per symbol = %d" % self.bits_per_symbol() + print "Gray code = %s" % self._gray_code + print "RRS roll-off factor = %f" % self._excess_bw + + def _setup_logging(self): + print "Modulation logging turned on." + self._fg.connect(self.bytes2chunks, + gr.file_sink(gr.sizeof_char, "bytes2chunks.dat")) + self._fg.connect(self.symbol_mapper, + gr.file_sink(gr.sizeof_char, "graycoder.dat")) + self._fg.connect(self.diffenc, + gr.file_sink(gr.sizeof_char, "diffenc.dat")) + self._fg.connect(self.chunks2symbols, + gr.file_sink(gr.sizeof_gr_complex, "chunks2symbols.dat")) + self._fg.connect(self.rrc_filter, + gr.file_sink(gr.sizeof_gr_complex, "rrc_filter.dat")) + + def add_options(parser): + """ + Adds QPSK modulation-specific options to the standard parser + """ + parser.add_option("", "--excess-bw", type="float", default=_def_excess_bw, + help="set RRC excess bandwith factor [default=%default] (PSK)") + parser.add_option("", "--no-gray-code", dest="gray_code", + action="store_false", default=_def_gray_code, + help="disable gray coding on modulated bits (PSK)") + add_options=staticmethod(add_options) + + + def extract_kwargs_from_options(options): + """ + Given command line options, create dictionary suitable for passing to __init__ + """ + return modulation_utils.extract_kwargs_from_options(dqpsk_mod.__init__, + ('self', 'fg'), options) + extract_kwargs_from_options=staticmethod(extract_kwargs_from_options) + + +# ///////////////////////////////////////////////////////////////////////////// +# DQPSK demodulator +# +# Differentially coherent detection of differentially encoded qpsk +# ///////////////////////////////////////////////////////////////////////////// + +class dqpsk_demod(gr.hier_block): + + def __init__(self, fg, + samples_per_symbol=_def_samples_per_symbol, + excess_bw=_def_excess_bw, + costas_alpha=_def_costas_alpha, + gain_mu=_def_gain_mu, + mu=_def_mu, + omega_relative_limit=_def_omega_relative_limit, + gray_code=_def_gray_code, + verbose=_def_verbose, + log=_def_log): + """ + Hierarchical block for RRC-filtered DQPSK demodulation + + The input is the complex modulated signal at baseband. + The output is a stream of bits packed 1 bit per byte (LSB) + + @param fg: flow graph + @type fg: flow graph + @param samples_per_symbol: samples per symbol >= 2 + @type samples_per_symbol: float + @param excess_bw: Root-raised cosine filter excess bandwidth + @type excess_bw: float + @param costas_alpha: loop filter gain + @type costas_alphas: float + @param gain_mu: for M&M block + @type gain_mu: float + @param mu: for M&M block + @type mu: float + @param omega_relative_limit: for M&M block + @type omega_relative_limit: float + @param gray_code: Tell modulator to Gray code the bits + @type gray_code: bool + @param verbose: Print information about modulator? + @type verbose: bool + @param debug: Print modualtion data to files? + @type debug: bool + """ + + self._fg = fg + self._samples_per_symbol = samples_per_symbol + self._excess_bw = excess_bw + self._costas_alpha = costas_alpha + self._gain_mu = gain_mu + self._mu = mu + self._omega_relative_limit = omega_relative_limit + self._gray_code = gray_code + + if samples_per_symbol < 2: + raise TypeError, "sbp must be >= 2, is %d" % samples_per_symbol + + arity = pow(2,self.bits_per_symbol()) + + # Automatic gain control + scale = (1.0/16384.0) + self.pre_scaler = gr.multiply_const_cc(scale) # scale the signal from full-range to +-1 + #self.agc = gr.agc2_cc(0.6e-1, 1e-3, 1, 1, 100) + self.agc = gr.feedforward_agc_cc(16, 1.0) + + # Costas loop (carrier tracking) + if self._costas_alpha is None: # If no alpha value was specified by the user + alpha_dir = {2:0.075, 3:0.09, 4:0.09, 5:0.095, 6:0.10, 7:0.105} + self._costas_alpha = alpha_dir[self._samples_per_symbol] + + costas_order = 4 + # The value of beta is now set to be underdamped; this value can have a huge impact on the + # performance of QPSK. Set to 0.25 for critically damped or higher for underdamped responses. + beta = .35 * self._costas_alpha * self._costas_alpha + self.costas_loop = gr.costas_loop_cc(self._costas_alpha, beta, 0.02, -0.02, costas_order) + + # RRC data filter + ntaps = 11 * samples_per_symbol + self.rrc_taps = gr.firdes.root_raised_cosine( + self._samples_per_symbol, # gain + self._samples_per_symbol, # sampling rate + 1.0, # symbol rate + self._excess_bw, # excess bandwidth (roll-off factor) + ntaps) + + self.rrc_filter=gr.fir_filter_ccf(1, self.rrc_taps) + + # symbol clock recovery + omega = self._samples_per_symbol + gain_omega = .25 * self._gain_mu * self._gain_mu + self.clock_recovery=gr.clock_recovery_mm_cc(omega, gain_omega, + self._mu, self._gain_mu, + self._omega_relative_limit) + + self.diffdec = gr.diff_phasor_cc() + #self.diffdec = gr.diff_decoder_bb(arity) + + # find closest constellation point + rot = 1 + #rot = .707 + .707j + rotated_const = map(lambda pt: pt * rot, psk.constellation[arity]) + #print "rotated_const = %s" % rotated_const + + self.slicer = gr.constellation_decoder_cb(rotated_const, range(arity)) + + if self._gray_code: + self.symbol_mapper = gr.map_bb(psk.gray_to_binary[arity]) + else: + self.symbol_mapper = gr.map_bb(psk.ungray_to_binary[arity]) + + + # unpack the k bit vector into a stream of bits + self.unpack = gr.unpack_k_bits_bb(self.bits_per_symbol()) + + if verbose: + self._print_verbage() + + if log: + self._setup_logging() + + # Connect & Initialize base class + self._fg.connect(self.pre_scaler, self.agc, self.costas_loop, + self.rrc_filter, self.clock_recovery, + self.diffdec, self.slicer, self.symbol_mapper, + self.unpack) + gr.hier_block.__init__(self, self._fg, self.pre_scaler, self.unpack) + + def samples_per_symbol(self): + return self._samples_per_symbol + + def bits_per_symbol(self=None): # staticmethod that's also callable on an instance + return 2 + bits_per_symbol = staticmethod(bits_per_symbol) # make it a static method. RTFM + + def _print_verbage(self): + print "bits per symbol = %d" % self.bits_per_symbol() + print "Gray code = %s" % self._gray_code + print "RRC roll-off factor = %.2f" % self._excess_bw + print "Costas Loop alpha = %.5f" % self._costas_alpha + print "M&M symbol sync gain = %.5f" % self._gain_mu + print "M&M symbol sync mu = %.5f" % self._mu + print "M&M omega relative limit = %.5f" % self._omega_relative_limit + + + def _setup_logging(self): + print "Modulation logging turned on." + self._fg.connect(self.pre_scaler, + gr.file_sink(gr.sizeof_gr_complex, "prescaler.dat")) + self._fg.connect(self.agc, + gr.file_sink(gr.sizeof_gr_complex, "agc.dat")) + self._fg.connect(self.costas_loop, + gr.file_sink(gr.sizeof_gr_complex, "costas_loop.dat")) + self._fg.connect((self.costas_loop,1), + gr.file_sink(gr.sizeof_gr_complex, "costas_error.dat")) + self._fg.connect(self.rrc_filter, + gr.file_sink(gr.sizeof_gr_complex, "rrc_filter.dat")) + self._fg.connect(self.clock_recovery, + gr.file_sink(gr.sizeof_gr_complex, "clock_recovery.dat")) + self._fg.connect((self.clock_recovery,1), + gr.file_sink(gr.sizeof_gr_complex, "clock_recovery_error.dat")) + self._fg.connect(self.diffdec, + gr.file_sink(gr.sizeof_gr_complex, "diffdec.dat")) + self._fg.connect(self.slicer, + gr.file_sink(gr.sizeof_char, "slicer.dat")) + self._fg.connect(self.symbol_mapper, + gr.file_sink(gr.sizeof_char, "gray_decoder.dat")) + self._fg.connect(self.unpack, + gr.file_sink(gr.sizeof_char, "unpack.dat")) + + def add_options(parser): + """ + Adds modulation-specific options to the standard parser + """ + parser.add_option("", "--excess-bw", type="float", default=_def_excess_bw, + help="set RRC excess bandwith factor [default=%default] (PSK)") + parser.add_option("", "--no-gray-code", dest="gray_code", + action="store_false", default=_def_gray_code, + help="disable gray coding on modulated bits (PSK)") + parser.add_option("", "--costas-alpha", type="float", default=None, + help="set Costas loop alpha value [default=%default] (PSK)") + parser.add_option("", "--gain-mu", type="float", default=_def_gain_mu, + help="set M&M symbol sync loop gain mu value [default=%default] (PSK)") + parser.add_option("", "--mu", type="float", default=_def_mu, + help="set M&M symbol sync loop mu value [default=%default] (PSK)") + add_options=staticmethod(add_options) + + def extract_kwargs_from_options(options): + """ + Given command line options, create dictionary suitable for passing to __init__ + """ + return modulation_utils.extract_kwargs_from_options( + dqpsk_demod.__init__, ('self', 'fg'), options) + extract_kwargs_from_options=staticmethod(extract_kwargs_from_options) + + +# +# Add these to the mod/demod registry +# +modulation_utils.add_type_1_mod('dqpsk', dqpsk_mod) +modulation_utils.add_type_1_demod('dqpsk', dqpsk_demod) Index: gnuradio-examples/python/qpsk_fpga/commandline_rx_realtime_usrp1_rxB_dbsrx_alpha0.2_bitrate_4M_freq_900MHz.sh =================================================================== --- gnuradio-examples/python/qpsk_fpga/commandline_rx_realtime_usrp1_rxB_dbsrx_alpha0.2_bitrate_4M_freq_900MHz.sh (revision 0) +++ gnuradio-examples/python/qpsk_fpga/commandline_rx_realtime_usrp1_rxB_dbsrx_alpha0.2_bitrate_4M_freq_900MHz.sh (revision 0) @@ -0,0 +1,2 @@ +#!/bin/sh +./benchmark_rx_qpsk_fpga.py -m dqpsk -R B -f 900.0e6 -F usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf --excess-bw 0.2 -r 4000000 --rx-gain 30 -u 1 Property changes on: gnuradio-examples/python/qpsk_fpga/commandline_rx_realtime_usrp1_rxB_dbsrx_alpha0.2_bitrate_4M_freq_900MHz.sh ___________________________________________________________________ Name: svn:executable + * Index: gnuradio-examples/python/qpsk_fpga/benchmark_rx_qpsk_fpga.py =================================================================== --- gnuradio-examples/python/qpsk_fpga/benchmark_rx_qpsk_fpga.py (revision 0) +++ gnuradio-examples/python/qpsk_fpga/benchmark_rx_qpsk_fpga.py (revision 0) @@ -0,0 +1,115 @@ +#!/usr/bin/env python +# +# Copyright 2005,2006 Free Software Foundation, Inc. +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +from gnuradio import gr, gru, modulation_utils +from gnuradio import usrp +from gnuradio import eng_notation +from gnuradio.eng_option import eng_option +from optparse import OptionParser + +import random +import struct +import sys + +# from current dir +#from receive_path import receive_path +from receive_path_qpsk_fpga import receive_path_qpsk_fpga +import fusb_options + +#import os +#print os.getpid() +#raw_input('Attach and press enter: ') + + +class my_graph(gr.flow_graph): + + def __init__(self, demod_class, rx_callback, options): + gr.flow_graph.__init__(self) + self.rxpath = receive_path_qpsk_fpga(self, demod_class, rx_callback, options) + +# ///////////////////////////////////////////////////////////////////////////// +# main +# ///////////////////////////////////////////////////////////////////////////// + +global n_rcvd, n_right + +def main(): + global n_rcvd, n_right + + n_rcvd = 0 + n_right = 0 + + def rx_callback(ok, payload): + global n_rcvd, n_right + (pktno,) = struct.unpack('!H', payload[0:2]) + n_rcvd += 1 + if ok: + n_right += 1 + + print "ok = %5s pktno = %4d n_rcvd = %4d n_right = %4d" % ( + ok, pktno, n_rcvd, n_right) + + + demods = modulation_utils.type_1_demods() + + # Create Options Parser: + parser = OptionParser (option_class=eng_option, conflict_handler="resolve") + expert_grp = parser.add_option_group("Expert") + + parser.add_option("-m", "--modulation", type="choice", choices=demods.keys(), + default='gmsk', + help="Select modulation from: %s [default=%%default]" + % (', '.join(demods.keys()),)) + + receive_path_qpsk_fpga.add_options(parser, expert_grp) + + for mod in demods.values(): + mod.add_options(expert_grp) + + fusb_options.add_options(expert_grp) + (options, args) = parser.parse_args () + + if len(args) != 0: + parser.print_help(sys.stderr) + sys.exit(1) + + if options.rx_freq is None: + sys.stderr.write("You must specify -f FREQ or --freq FREQ\n") + parser.print_help(sys.stderr) + sys.exit(1) + + + # build the graph + fg = my_graph(demods[options.modulation], rx_callback, options) + + r = gr.enable_realtime_scheduling() + if r != gr.RT_OK: + print "Warning: Failed to enable realtime scheduling." + + fg.start() # start flow graph + fg.wait() # wait for it to finish + +if __name__ == '__main__': + try: + main() + except KeyboardInterrupt: + pass Index: gnuradio-examples/python/qpsk_fpga/benchmark_tx_qpsk_fpga.py =================================================================== --- gnuradio-examples/python/qpsk_fpga/benchmark_tx_qpsk_fpga.py (revision 0) +++ gnuradio-examples/python/qpsk_fpga/benchmark_tx_qpsk_fpga.py (revision 0) @@ -0,0 +1,128 @@ +#!/usr/bin/env python +# +# Copyright 2005, 2006 Free Software Foundation, Inc. +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +from gnuradio import gr, gru, modulation_utils +from gnuradio import usrp +from gnuradio import eng_notation +from gnuradio.eng_option import eng_option +from optparse import OptionParser +import dqpsk_fpga + +import random, time, struct, sys + +# from current dir +from transmit_path_qpsk_fpga import transmit_path_qpsk_fpga +import fusb_options + +#import os +#print os.getpid() +#raw_input('Attach and press enter') + + +class my_graph(gr.flow_graph): + def __init__(self, modulator_class, options): + gr.flow_graph.__init__(self) + self.txpath = transmit_path_qpsk_fpga(self, modulator_class, options) + + +# ///////////////////////////////////////////////////////////////////////////// +# main +# ///////////////////////////////////////////////////////////////////////////// + +def main(): + + def send_pkt(payload='', eof=False): + return fg.txpath.send_pkt(payload, eof) + + def rx_callback(ok, payload): + print "ok = %r, payload = '%s'" % (ok, payload) + + mods = modulation_utils.type_1_mods() + + parser = OptionParser(option_class=eng_option, conflict_handler="resolve") + expert_grp = parser.add_option_group("Expert") + + parser.add_option("-m", "--modulation", type="choice", choices=mods.keys(), + default='dqpsk_fpga', + help="Select modulation, only dqpsk_fpga is valid for this script [default=dqpsk_fpga]") + #Select modulation from: %s [default=%%default]" + # % (', '.join(mods.keys()),)) + + parser.add_option("-s", "--size", type="eng_float", default=1024,#2027,1500, + help="set packet size [default=%default]") + parser.add_option("-M", "--megabytes", type="eng_float", default=100.0,#1.0, + help="set megabytes to transmit [default=%default]") + parser.add_option("","--discontinuous", action="store_true", default=False, + help="enable discontinous transmission (bursts of 5 packets)") + + transmit_path_qpsk_fpga.add_options(parser, expert_grp) + + for mod in mods.values(): + mod.add_options(expert_grp) + + fusb_options.add_options(expert_grp) + if parser.has_option("--excess-bw"): + parser.remove_option("--excess-bw") #excess-bw or alpha is hardcoded in the selected FPGA firmware + (options, args) = parser.parse_args () + + if len(args) != 0: + parser.print_help() + sys.exit(1) + + if options.tx_freq is None: + sys.stderr.write("You must specify -f FREQ or --freq FREQ\n") + parser.print_help(sys.stderr) + sys.exit(1) + + # build the graph + print "mods[options.modulation]",mods[options.modulation] + fg = my_graph(mods[options.modulation], options) + + r = gr.enable_realtime_scheduling() + if r != gr.RT_OK: + print "Warning: failed to enable realtime scheduling" + + fg.start() # start flow graph + + + # generate and send packets + nbytes = int(1e6 * options.megabytes) + n = 0 + pktno = 0 + pkt_size = int(options.size) + + while n < nbytes: + send_pkt(struct.pack('!H', pktno) + (pkt_size - 2) * chr(pktno & 0xff)) + n += pkt_size + sys.stderr.write('.') + if options.discontinuous and pktno % 5 == 4: + time.sleep(1) + pktno += 1 + + send_pkt(eof=True) + fg.wait() # wait for it to finish + +if __name__ == '__main__': + try: + main() + except KeyboardInterrupt: + pass Index: gnuradio-examples/python/qpsk_fpga/commandline_tx_txA_basicTX_alpha_0.35_bitrate_4M_freq_16MHz.sh =================================================================== --- gnuradio-examples/python/qpsk_fpga/commandline_tx_txA_basicTX_alpha_0.35_bitrate_4M_freq_16MHz.sh (revision 0) +++ gnuradio-examples/python/qpsk_fpga/commandline_tx_txA_basicTX_alpha_0.35_bitrate_4M_freq_16MHz.sh (revision 0) @@ -0,0 +1,2 @@ +#!/bin/sh +./benchmark_tx_qpsk_fpga.py -T A -f 16.0e6 -v -F usrp_frac_interp_2rxhb_2tx_alpha0.35_int16_dec1_DACint4X.rbf -I 16 -D 1 Property changes on: gnuradio-examples/python/qpsk_fpga/commandline_tx_txA_basicTX_alpha_0.35_bitrate_4M_freq_16MHz.sh ___________________________________________________________________ Name: svn:executable + * Index: gnuradio-examples/python/qpsk_fpga/commandline_rx_file_usrp0_rxB_rfx900_freq_900MHz_alpha_0.35_bitrate_4M.sh =================================================================== --- gnuradio-examples/python/qpsk_fpga/commandline_rx_file_usrp0_rxB_rfx900_freq_900MHz_alpha_0.35_bitrate_4M.sh (revision 0) +++ gnuradio-examples/python/qpsk_fpga/commandline_rx_file_usrp0_rxB_rfx900_freq_900MHz_alpha_0.35_bitrate_4M.sh (revision 0) @@ -0,0 +1,4 @@ +#!/bin/sh +./usrp_rx_cfile_fpga.py -u 0 -R B -d 16 -f 900.0e6 -F usrp_frac_interp_2rxhb_2tx_alpha0.35_int16_dec1_DACint4X.rbf -g 30 -N 10000000 data_cfloat.raw +./benchmark_rx_qpsk_file.py -m dqpsk -d 16 -f 0 -S 2 -r 40000000 -v --excess-bw=0.35 + Property changes on: gnuradio-examples/python/qpsk_fpga/commandline_rx_file_usrp0_rxB_rfx900_freq_900MHz_alpha_0.35_bitrate_4M.sh ___________________________________________________________________ Name: svn:executable + * Index: gnuradio-examples/python/qpsk_fpga/usrp_rx_cfile_basicrxcomplex_fpga.py =================================================================== --- gnuradio-examples/python/qpsk_fpga/usrp_rx_cfile_basicrxcomplex_fpga.py (revision 0) +++ gnuradio-examples/python/qpsk_fpga/usrp_rx_cfile_basicrxcomplex_fpga.py (revision 0) @@ -0,0 +1,114 @@ +#!/usr/bin/env python + +""" +Read samples from the USRP and write to file formatted as binary +outputs single precision complex float values or complex short values (interleaved 16 bit signed short integers). + +""" + +from gnuradio import gr, eng_notation +from gnuradio import audio +from gnuradio import usrp +from gnuradio.eng_option import eng_option +from optparse import OptionParser + +class my_graph(gr.flow_graph): + + def __init__(self): + gr.flow_graph.__init__(self) + + usage="%prog: [options] output_filename" + parser = OptionParser(option_class=eng_option, usage=usage) + parser.add_option("-u", "--usrp", type="int", default=0, + help="which usrp to use (0, 1, 2 ...) [default=0]") + parser.add_option("-R", "--rx-subdev-spec", type="subdev", default=(0, 0), + help="select USRP Rx side A or B (default=A)") + parser.add_option("-d", "--decim", type="int", default=16, + help="set fgpa decimation rate to DECIM [default=%default]") + parser.add_option("-f", "--freq", type="eng_float", default=None, + help="set frequency to FREQ", metavar="FREQ") + parser.add_option("-F", "--fpga", default="std_2rxhb_2tx.rbf", + help="set fpga_filename to FPGA [default=%default]") + parser.add_option("-g", "--gain", type="eng_float", default=None, + help="set gain in dB (default is midpoint)") + parser.add_option("-8", "--width-8", action="store_true", default=False, + help="Enable 8-bit samples across USB") + parser.add_option( "--no-hb", action="store_true", default=False, + help="don't use halfband filter in usrp") + parser.add_option( "-s","--output-shorts", action="store_true", default=False, + help="output interleaved shorts in stead of complex floats") + parser.add_option("-N", "--nsamples", type="eng_float", default=None, + help="number of samples to collect [default=+inf]") + (options, args) = parser.parse_args () + if len(args) != 1: + parser.print_help() + raise SystemExit, 1 + filename = args[0] + + if options.freq is None: + parser.print_help() + sys.stderr.write('You must specify the frequency with -f FREQ\n'); + raise SystemExit, 1 + + # build the graph + if options.no_hb or (options.decim<8): + if options.fpga=="std_2rxhb_2tx.rbf": + self.fpga_filename="std_4rx_0tx.rbf" #Min decimation of this firmware is 4. contains 4 Rx paths without halfbands and 0 tx paths. + else: + self.fpga_filename=options.fpga + if options.output_shorts: + self.u = usrp.source_s(options.usrp,decim_rate=options.decim,fpga_filename=self.fpga_filename) + else: + self.u = usrp.source_c(options.usrp,decim_rate=options.decim,fpga_filename=self.fpga_filename) + else: + #standard fpga firmware "std_2rxhb_2tx.rbf" contains 2 Rx paths with halfband filters and 2 tx paths (the default) min decimation 8 + if options.output_shorts: + self.u = usrp.source_s(options.usrp,decim_rate=options.decim,fpga_filename=options.fpga) + else: + self.u = usrp.source_c(options.usrp,decim_rate=options.decim,fpga_filename=options.fpga) + if options.width_8: + sample_width = 8 + sample_shift = 8 + format = self.u.make_format(sample_width, sample_shift) + r = self.u.set_format(format) + if options.output_shorts: + self.dst = gr.file_sink(gr.sizeof_short, filename) + else: + self.dst = gr.file_sink(gr.sizeof_gr_complex, filename) + if options.nsamples is None: + self.connect(self.u, self.dst) + else: + if options.output_shorts: + self.head = gr.head(gr.sizeof_short, int(options.nsamples)*2) + else: + self.head = gr.head(gr.sizeof_gr_complex, int(options.nsamples)) + self.connect(self.u, self.head, self.dst) + + if options.rx_subdev_spec is None: + options.rx_subdev_spec = usrp.pick_rx_subdevice(self.u) + self.u.set_mux(0x32103210) #usrp.determine_rx_mux_value(self.u, options.rx_subdev_spec)) + + # determine the daughterboard subdevice we're using + self.subdev = usrp.selected_subdev(self.u, options.rx_subdev_spec) + print "Using RX d'board %s" % (self.subdev.side_and_name(),) + input_rate = self.u.adc_freq() / self.u.decim_rate() + print "USB sample rate %s" % (eng_notation.num_to_str(input_rate)) + + if options.gain is None: + # if no gain was specified, use the mid-point in dB + g = self.subdev.gain_range() + options.gain = float(g[0]+g[1])/2 + + self.subdev.set_gain(options.gain) + + r = self.u.tune(0, self.subdev, options.freq) + if not r: + sys.stderr.write('Failed to set frequency\n') + raise SystemExit, 1 + + +if __name__ == '__main__': + try: + my_graph().run() + except KeyboardInterrupt: + pass Index: gnuradio-examples/python/qpsk_fpga/commandline_rx_file_usrp1_rxB_rfx900_freq_900MHz_alpha_0.35_bitrate_4M.sh =================================================================== --- gnuradio-examples/python/qpsk_fpga/commandline_rx_file_usrp1_rxB_rfx900_freq_900MHz_alpha_0.35_bitrate_4M.sh (revision 0) +++ gnuradio-examples/python/qpsk_fpga/commandline_rx_file_usrp1_rxB_rfx900_freq_900MHz_alpha_0.35_bitrate_4M.sh (revision 0) @@ -0,0 +1,4 @@ +#!/bin/sh +./usrp_rx_cfile_fpga.py -u 1 -R B -d 16 -f 900.0e6 -F usrp_frac_interp_2rxhb_2tx_alpha0.35_int16_dec1_DACint4X.rbf -g 30 -N 10000000 data_cfloat.raw +./benchmark_rx_qpsk_file.py -m dqpsk -d 16 -f 0 -S 2 -r 40000000 -v --excess-bw=0.35 + Property changes on: gnuradio-examples/python/qpsk_fpga/commandline_rx_file_usrp1_rxB_rfx900_freq_900MHz_alpha_0.35_bitrate_4M.sh ___________________________________________________________________ Name: svn:executable + * Index: gnuradio-examples/python/qpsk_fpga/commandline_tx_txA_basicTX_alpha_0.2_bitrate_4M_freq_0Hz.sh =================================================================== --- gnuradio-examples/python/qpsk_fpga/commandline_tx_txA_basicTX_alpha_0.2_bitrate_4M_freq_0Hz.sh (revision 0) +++ gnuradio-examples/python/qpsk_fpga/commandline_tx_txA_basicTX_alpha_0.2_bitrate_4M_freq_0Hz.sh (revision 0) @@ -0,0 +1,2 @@ +#!/bin/sh +./benchmark_tx_qpsk_fpga.py -T A -f 0.0e6 -v -F usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf -I 16 -D 1 Property changes on: gnuradio-examples/python/qpsk_fpga/commandline_tx_txA_basicTX_alpha_0.2_bitrate_4M_freq_0Hz.sh ___________________________________________________________________ Name: svn:executable + * Index: gnuradio-examples/python/qpsk_fpga/fusb_options.py =================================================================== --- gnuradio-examples/python/qpsk_fpga/fusb_options.py (revision 0) +++ gnuradio-examples/python/qpsk_fpga/fusb_options.py (revision 0) @@ -0,0 +1,31 @@ +# +# Copyright 2006 Free Software Foundation, Inc. +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +def add_options(parser): + """ + Add Fast USB specifc options to command line parser. + + @param parser: instance of OptionParser + """ + parser.add_option("-B", "--fusb-block-size", type="int", default=0, + help="specify fast usb block size [default=%default]") + parser.add_option("-N", "--fusb-nblocks", type="int", default=0, + help="specify number of fast usb blocks [default=%default]") Index: gnuradio-examples/python/qpsk_fpga/commandline_tx_txA_basicTX_alpha_0.2_bitrate_4M_freq_16MHz.sh =================================================================== --- gnuradio-examples/python/qpsk_fpga/commandline_tx_txA_basicTX_alpha_0.2_bitrate_4M_freq_16MHz.sh (revision 0) +++ gnuradio-examples/python/qpsk_fpga/commandline_tx_txA_basicTX_alpha_0.2_bitrate_4M_freq_16MHz.sh (revision 0) @@ -0,0 +1,2 @@ +#!/bin/sh +./benchmark_tx_qpsk_fpga.py -T A -f 16.0e6 -v -F usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf -I 16 -D 1 Property changes on: gnuradio-examples/python/qpsk_fpga/commandline_tx_txA_basicTX_alpha_0.2_bitrate_4M_freq_16MHz.sh ___________________________________________________________________ Name: svn:executable + * Index: gnuradio-examples/python/qpsk_fpga/commandline_rx_file_usrp0_rxB_rfx900_freq_900MHz_alpha_0.2_bitrate_4M.sh =================================================================== --- gnuradio-examples/python/qpsk_fpga/commandline_rx_file_usrp0_rxB_rfx900_freq_900MHz_alpha_0.2_bitrate_4M.sh (revision 0) +++ gnuradio-examples/python/qpsk_fpga/commandline_rx_file_usrp0_rxB_rfx900_freq_900MHz_alpha_0.2_bitrate_4M.sh (revision 0) @@ -0,0 +1,4 @@ +#!/bin/sh +./usrp_rx_cfile_fpga.py -u 0 -R B -d 16 -f 900.0e6 -F usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf -g 30 -N 10000000 data_cfloat.raw +./benchmark_rx_qpsk_file.py -m dqpsk -d 16 -f 0 -S 2 -r 40000000 -v --excess-bw=0.2 + Property changes on: gnuradio-examples/python/qpsk_fpga/commandline_rx_file_usrp0_rxB_rfx900_freq_900MHz_alpha_0.2_bitrate_4M.sh ___________________________________________________________________ Name: svn:executable + * Index: gnuradio-examples/python/qpsk_fpga/commandline_tx_txA_rfx900_alpha_0.35_bitrate_4M_freq_900Mhz.sh =================================================================== --- gnuradio-examples/python/qpsk_fpga/commandline_tx_txA_rfx900_alpha_0.35_bitrate_4M_freq_900Mhz.sh (revision 0) +++ gnuradio-examples/python/qpsk_fpga/commandline_tx_txA_rfx900_alpha_0.35_bitrate_4M_freq_900Mhz.sh (revision 0) @@ -0,0 +1,2 @@ +#!/bin/sh +./benchmark_tx_qpsk_fpga.py -T A -f 900.0e6 -v -F usrp_frac_interp_2rxhb_2tx_alpha0.35_int16_dec1_DACint4X.rbf -I 16 -D 1 Property changes on: gnuradio-examples/python/qpsk_fpga/commandline_tx_txA_rfx900_alpha_0.35_bitrate_4M_freq_900Mhz.sh ___________________________________________________________________ Name: svn:executable + * Index: gnuradio-examples/python/qpsk_fpga/dqpsk_fpga.py =================================================================== --- gnuradio-examples/python/qpsk_fpga/dqpsk_fpga.py (revision 0) +++ gnuradio-examples/python/qpsk_fpga/dqpsk_fpga.py (revision 0) @@ -0,0 +1,387 @@ +# +# Copyright 2005,2006 Free Software Foundation, Inc. +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +# See gnuradio-examples/python/gmsk2 for examples + +""" +differential QPSK modulation and demodulation. +""" + +from gnuradio import gr, gru, modulation_utils +from math import pi, sqrt +import gnuradio.blksimpl.psk as psk +import cmath +import Numeric +from pprint import pprint + +# default values (used in __init__ and add_options) +_def_samples_per_symbol = 2 +_def_excess_bw = 0.35 +_def_gray_code = True +_def_verbose = False +_def_log = False + +_def_costas_alpha = None +_def_gain_mu = 0.03 +_def_mu = 0.05 +_def_omega_relative_limit = 0.005 + + +# ///////////////////////////////////////////////////////////////////////////// +# DQPSK modulator +# ///////////////////////////////////////////////////////////////////////////// + +class dqpsk_fpga_mod(gr.hier_block): + + def __init__(self, fg, + samples_per_symbol=_def_samples_per_symbol, + excess_bw=_def_excess_bw, + gray_code=_def_gray_code, + verbose=_def_verbose, + log=_def_log): + """ + Hierarchical block for RRC-filtered QPSK modulation. + + The input is a byte stream (unsigned char) and the + output is the complex modulated signal at baseband. + + @param fg: flow graph + @type fg: flow graph + @param samples_per_symbol: samples per symbol >= 2 + @type samples_per_symbol: integer + @param excess_bw: Root-raised cosine filter excess bandwidth + @type excess_bw: float + @param gray_code: Tell modulator to Gray code the bits + @type gray_code: bool + @param verbose: Print information about modulator? + @type verbose: bool + @param debug: Print modualtion data to files? + @type debug: bool + """ + + self._fg = fg + self._samples_per_symbol = samples_per_symbol + self._excess_bw = excess_bw + self._gray_code = gray_code + assert (self.bits_per_symbol()==2) #can only do qpsk + #if not isinstance(samples_per_symbol, int) or samples_per_symbol < 2: + # raise TypeError, ("sbp must be an integer >= 2, is %d" % samples_per_symbol) + + ntaps = 11 * samples_per_symbol + + arity = pow(2,self.bits_per_symbol()) + + # turn bytes into k-bit vectors + self.bytes2chunks = \ + gr.packed_to_unpacked_bb(self.bits_per_symbol(), gr.GR_MSB_FIRST) + + if self._gray_code: + self.symbol_mapper = gr.map_bb(psk.binary_to_gray[arity]) + else: + self.symbol_mapper = gr.map_bb(psk.binary_to_ungray[arity]) + + self.diffenc = gr.diff_encoder_bb(arity) + + rot = .707 + .707j + rotated_const = map(lambda pt: pt * rot, psk.constellation[arity]) + print rotated_const + #self.chunks2symbols = gr.chunks_to_symbols_bc(rotated_const) + self.chunks2symbols = gr.map_bb((3,1,0,2)) + # pulse shaping filter + #self.rrc_taps = gr.firdes.root_raised_cosine( + # self._samples_per_symbol, # gain (sps since we're interpolating by sps) + # self._samples_per_symbol, # sampling rate + # 1.0, # symbol rate + # self._excess_bw, # excess bandwidth (roll-off factor) + # ntaps) + + #self.rrc_filter = gr.interp_fir_filter_ccf(self._samples_per_symbol, self.rrc_taps) + + if verbose: + self._print_verbage() + + if log: + self._setup_logging() + self.unpackbits=gr.unpack_k_bits_bb (self.bits_per_symbol()) # self.bits_per_symbol() must be 2 + self.split=gr.deinterleave (1) #split into i and q (still 1 bit) + self.packbits_i=gr.unpacked_to_packed_bb (1, gr.GR_LSB_FIRST)#(unsigned int bits_per_chunk, gr_endianness_t endianness GR_MSB_FIRST or GR_LSB_FIRST ) + self.packbytes_i=gr.stream_to_vector(1,2) + self.packbits_q=gr.unpacked_to_packed_bb (1, gr.GR_LSB_FIRST)#(unsigned int bits_per_chunk, gr_endianness_t endianness GR_MSB_FIRST or GR_LSB_FIRST ) + self.packbytes_q=gr.stream_to_vector(1,2) + self.interleave=gr.interleave(2) + # Connect & Initialize base class + self._fg.connect(self.bytes2chunks, self.symbol_mapper, self.diffenc,self.chunks2symbols, + self.unpackbits,self.split) + self._fg.connect((self.split,0),self.packbits_q,self.packbytes_q) + self._fg.connect((self.split,1),self.packbits_i,self.packbytes_i) + + self._fg.connect(self.packbytes_q,(self.interleave,0)) + self._fg.connect(self.packbytes_i,(self.interleave,1)) + # self.chunks2symbols, self.rrc_filter) + gr.hier_block.__init__(self, self._fg, self.bytes2chunks, self.interleave) + + def samples_per_symbol(self): + return self._samples_per_symbol + + def bits_per_symbol(self=None): # staticmethod that's also callable on an instance + return 2 + bits_per_symbol = staticmethod(bits_per_symbol) # make it a static method. RTFM + + def _print_verbage(self): + print "bits per symbol = %d" % self.bits_per_symbol() + print "Gray code = %s" % self._gray_code + #print "RRS roll-off factor = %f" % self._excess_bw + + def _setup_logging(self): + print "Modulation logging turned on." + self._fg.connect(self.bytes2chunks, + gr.file_sink(gr.sizeof_char, "bytes2chunks.dat")) + self._fg.connect(self.symbol_mapper, + gr.file_sink(gr.sizeof_char, "graycoder.dat")) + self._fg.connect(self.diffenc, + gr.file_sink(gr.sizeof_char, "diffenc.dat")) + self._fg.connect(self.chunks2symbols, + gr.file_sink(gr.sizeof_gr_complex, "chunks2symbols.dat")) + self._fg.connect(self.rrc_filter, + gr.file_sink(gr.sizeof_gr_complex, "rrc_filter.dat")) + + def add_options(parser): + """ + Adds QPSK modulation-specific options to the standard parser + """ + #parser.add_option("", "--excess-bw", type="float", default=_def_excess_bw, + # help="set RRC excess bandwith factor [default=%default] (PSK)") + parser.add_option("", "--no-gray-code", dest="gray_code", + action="store_false", default=_def_gray_code, + help="disable gray coding on modulated bits (PSK)") + add_options=staticmethod(add_options) + + + def extract_kwargs_from_options(options): + """ + Given command line options, create dictionary suitable for passing to __init__ + """ + return modulation_utils.extract_kwargs_from_options(dqpsk_fpga_mod.__init__, + ('self', 'fg'), options) + extract_kwargs_from_options=staticmethod(extract_kwargs_from_options) + + +# ///////////////////////////////////////////////////////////////////////////// +# DQPSK demodulator +# +# Differentially coherent detection of differentially encoded qpsk +# ///////////////////////////////////////////////////////////////////////////// + +class dqpsk_demod(gr.hier_block): + + def __init__(self, fg, + samples_per_symbol=_def_samples_per_symbol, + excess_bw=_def_excess_bw, + costas_alpha=_def_costas_alpha, + gain_mu=_def_gain_mu, + mu=_def_mu, + omega_relative_limit=_def_omega_relative_limit, + gray_code=_def_gray_code, + verbose=_def_verbose, + log=_def_log): + """ + Hierarchical block for RRC-filtered DQPSK demodulation + + The input is the complex modulated signal at baseband. + The output is a stream of bits packed 1 bit per byte (LSB) + + @param fg: flow graph + @type fg: flow graph + @param samples_per_symbol: samples per symbol >= 2 + @type samples_per_symbol: float + @param excess_bw: Root-raised cosine filter excess bandwidth + @type excess_bw: float + @param costas_alpha: loop filter gain + @type costas_alphas: float + @param gain_mu: for M&M block + @type gain_mu: float + @param mu: for M&M block + @type mu: float + @param omega_relative_limit: for M&M block + @type omega_relative_limit: float + @param gray_code: Tell modulator to Gray code the bits + @type gray_code: bool + @param verbose: Print information about modulator? + @type verbose: bool + @param debug: Print modualtion data to files? + @type debug: bool + """ + + self._fg = fg + self._samples_per_symbol = samples_per_symbol + self._excess_bw = excess_bw + self._costas_alpha = costas_alpha + self._gain_mu = gain_mu + self._mu = mu + self._omega_relative_limit = omega_relative_limit + self._gray_code = gray_code + + if samples_per_symbol < 2: + raise TypeError, "sbp must be >= 2, is %d" % samples_per_symbol + + arity = pow(2,self.bits_per_symbol()) + + # Automatic gain control + scale = (1.0/16384.0) + self.pre_scaler = gr.multiply_const_cc(scale) # scale the signal from full-range to +-1 + #self.agc = gr.agc2_cc(0.6e-1, 1e-3, 1, 1, 100) + self.agc = gr.feedforward_agc_cc(16, 1.0) + + # Costas loop (carrier tracking) + if self._costas_alpha is None: # If no alpha value was specified by the user + alpha_dir = {2:0.075, 3:0.09, 4:0.09, 5:0.095, 6:0.10, 7:0.105} + self._costas_alpha = alpha_dir[self._samples_per_symbol] + + costas_order = 4 + # The value of beta is now set to be underdamped; this value can have a huge impact on the + # performance of QPSK. Set to 0.25 for critically damped or higher for underdamped responses. + beta = .35 * self._costas_alpha * self._costas_alpha + self.costas_loop = gr.costas_loop_cc(self._costas_alpha, beta, 0.02, -0.02, costas_order) + + # RRC data filter + ntaps = 11 * samples_per_symbol + self.rrc_taps = gr.firdes.root_raised_cosine( + self._samples_per_symbol, # gain + self._samples_per_symbol, # sampling rate + 1.0, # symbol rate + self._excess_bw, # excess bandwidth (roll-off factor) + ntaps) + + self.rrc_filter=gr.fir_filter_ccf(1, self.rrc_taps) + + # symbol clock recovery + omega = self._samples_per_symbol + gain_omega = .25 * self._gain_mu * self._gain_mu + self.clock_recovery=gr.clock_recovery_mm_cc(omega, gain_omega, + self._mu, self._gain_mu, + self._omega_relative_limit) + + self.diffdec = gr.diff_phasor_cc() + #self.diffdec = gr.diff_decoder_bb(arity) + + # find closest constellation point + rot = 1 + #rot = .707 + .707j + rotated_const = map(lambda pt: pt * rot, psk.constellation[arity]) + #print "rotated_const = %s" % rotated_const + + self.slicer = gr.constellation_decoder_cb(rotated_const, range(arity)) + + if self._gray_code: + self.symbol_mapper = gr.map_bb(psk.gray_to_binary[arity]) + else: + self.symbol_mapper = gr.map_bb(psk.ungray_to_binary[arity]) + + + # unpack the k bit vector into a stream of bits + self.unpack = gr.unpack_k_bits_bb(self.bits_per_symbol()) + + if verbose: + self._print_verbage() + + if log: + self._setup_logging() + + # Connect & Initialize base class + self._fg.connect(self.pre_scaler, self.agc, self.costas_loop, + self.rrc_filter, self.clock_recovery, + self.diffdec, self.slicer, self.symbol_mapper, + self.unpack) + gr.hier_block.__init__(self, self._fg, self.pre_scaler, self.unpack) + + def samples_per_symbol(self): + return self._samples_per_symbol + + def bits_per_symbol(self=None): # staticmethod that's also callable on an instance + return 2 + bits_per_symbol = staticmethod(bits_per_symbol) # make it a static method. RTFM + + def _print_verbage(self): + print "bits per symbol = %d" % self.bits_per_symbol() + print "Gray code = %s" % self._gray_code + print "RRC roll-off factor = %.2f" % self._excess_bw + print "Costas Loop alpha = %.5f" % self._costas_alpha + print "M&M symbol sync gain = %.5f" % self._gain_mu + print "M&M symbol sync mu = %.5f" % self._mu + print "M&M omega relative limit = %.5f" % self._omega_relative_limit + + + def _setup_logging(self): + print "Modulation logging turned on." + self._fg.connect(self.pre_scaler, + gr.file_sink(gr.sizeof_gr_complex, "prescaler.dat")) + self._fg.connect(self.agc, + gr.file_sink(gr.sizeof_gr_complex, "agc.dat")) + self._fg.connect(self.costas_loop, + gr.file_sink(gr.sizeof_gr_complex, "costas_loop.dat")) + self._fg.connect((self.costas_loop,1), + gr.file_sink(gr.sizeof_gr_complex, "costas_error.dat")) + self._fg.connect(self.rrc_filter, + gr.file_sink(gr.sizeof_gr_complex, "rrc_filter.dat")) + self._fg.connect(self.clock_recovery, + gr.file_sink(gr.sizeof_gr_complex, "clock_recovery.dat")) + self._fg.connect((self.clock_recovery,1), + gr.file_sink(gr.sizeof_gr_complex, "clock_recovery_error.dat")) + self._fg.connect(self.diffdec, + gr.file_sink(gr.sizeof_gr_complex, "diffdec.dat")) + self._fg.connect(self.slicer, + gr.file_sink(gr.sizeof_char, "slicer.dat")) + self._fg.connect(self.symbol_mapper, + gr.file_sink(gr.sizeof_char, "gray_decoder.dat")) + self._fg.connect(self.unpack, + gr.file_sink(gr.sizeof_char, "unpack.dat")) + + def add_options(parser): + """ + Adds modulation-specific options to the standard parser + """ + parser.add_option("", "--excess-bw", type="float", default=_def_excess_bw, + help="set RRC excess bandwith factor [default=%default] (PSK)") + parser.add_option("", "--no-gray-code", dest="gray_code", + action="store_false", default=_def_gray_code, + help="disable gray coding on modulated bits (PSK)") + parser.add_option("", "--costas-alpha", type="float", default=None, + help="set Costas loop alpha value [default=%default] (PSK)") + parser.add_option("", "--gain-mu", type="float", default=_def_gain_mu, + help="set M&M symbol sync loop gain mu value [default=%default] (PSK)") + parser.add_option("", "--mu", type="float", default=_def_mu, + help="set M&M symbol sync loop mu value [default=%default] (PSK)") + add_options=staticmethod(add_options) + + def extract_kwargs_from_options(options): + """ + Given command line options, create dictionary suitable for passing to __init__ + """ + return modulation_utils.extract_kwargs_from_options( + dqpsk_demod.__init__, ('self', 'fg'), options) + extract_kwargs_from_options=staticmethod(extract_kwargs_from_options) + + +# +# Add these to the mod/demod registry +# +modulation_utils.add_type_1_mod('dqpsk_fpga', dqpsk_fpga_mod) +modulation_utils.add_type_1_demod('dqpsk', dqpsk_demod) Index: gnuradio-examples/python/qpsk_fpga/commandline_rx_realtime_usrp0_rxA_dbsrx_alpha0.35_bitrate_4M_freq_900MHz.sh =================================================================== --- gnuradio-examples/python/qpsk_fpga/commandline_rx_realtime_usrp0_rxA_dbsrx_alpha0.35_bitrate_4M_freq_900MHz.sh (revision 0) +++ gnuradio-examples/python/qpsk_fpga/commandline_rx_realtime_usrp0_rxA_dbsrx_alpha0.35_bitrate_4M_freq_900MHz.sh (revision 0) @@ -0,0 +1,2 @@ +#!/bin/sh +./benchmark_rx_qpsk_fpga.py -m dqpsk -R A -f 900.0e6 -F usrp_frac_interp_2rxhb_2tx_alpha0.35_int16_dec1_DACint4X.rbf --excess-bw 0.35 -r 4000000 --rx-gain 30 -u 0 Property changes on: gnuradio-examples/python/qpsk_fpga/commandline_rx_realtime_usrp0_rxA_dbsrx_alpha0.35_bitrate_4M_freq_900MHz.sh ___________________________________________________________________ Name: svn:executable + * Index: gnuradio-examples/python/qpsk_fpga/commandline_rx_realtime_usrp0_rxB_dbsrx_alpha0.35_bitrate_4M_freq_900MHz.sh =================================================================== --- gnuradio-examples/python/qpsk_fpga/commandline_rx_realtime_usrp0_rxB_dbsrx_alpha0.35_bitrate_4M_freq_900MHz.sh (revision 0) +++ gnuradio-examples/python/qpsk_fpga/commandline_rx_realtime_usrp0_rxB_dbsrx_alpha0.35_bitrate_4M_freq_900MHz.sh (revision 0) @@ -0,0 +1,2 @@ +#!/bin/sh +./benchmark_rx_qpsk_fpga.py -m dqpsk -R B -f 900.0e6 -F usrp_frac_interp_2rxhb_2tx_alpha0.35_int16_dec1_DACint4X.rbf --excess-bw 0.35 -r 4000000 --rx-gain 30 -u 0 Property changes on: gnuradio-examples/python/qpsk_fpga/commandline_rx_realtime_usrp0_rxB_dbsrx_alpha0.35_bitrate_4M_freq_900MHz.sh ___________________________________________________________________ Name: svn:executable + * Index: gnuradio-examples/python/qpsk_fpga/Makefile.am =================================================================== --- gnuradio-examples/python/qpsk_fpga/Makefile.am (revision 0) +++ gnuradio-examples/python/qpsk_fpga/Makefile.am (revision 0) @@ -0,0 +1,38 @@ +# +# Copyright 2007 Free Software Foundation, Inc. +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + + + +EXTRA_DIST = \ + README.txt \ + benchmark_rx_qpsk_file.py \ + benchmark_rx_qpsk_fpga.py \ + benchmark_tx_qpsk_fpga.py \ + commandline_examples.tar.gz \ + dqpsk_fpga.py \ + dqpsk_local.py \ + fusb_options.py \ + pick_bitrate.py \ + receive_path_qpsk_file.py \ + receive_path_qpsk_fpga.py \ + transmit_path_qpsk_fpga.py \ + usrp_rx_cfile_basicrxcomplex_fpga.py \ + usrp_rx_cfile_fpga.py Index: gnuradio-examples/python/qpsk_fpga/commandline_rx_realtime_usrp1_rxB_dbsrx_alpha0.35_bitrate_4M_freq_900MHz.sh =================================================================== --- gnuradio-examples/python/qpsk_fpga/commandline_rx_realtime_usrp1_rxB_dbsrx_alpha0.35_bitrate_4M_freq_900MHz.sh (revision 0) +++ gnuradio-examples/python/qpsk_fpga/commandline_rx_realtime_usrp1_rxB_dbsrx_alpha0.35_bitrate_4M_freq_900MHz.sh (revision 0) @@ -0,0 +1,2 @@ +#!/bin/sh +./benchmark_rx_qpsk_fpga.py -m dqpsk -R B -f 900.0e6 -F usrp_frac_interp_2rxhb_2tx_alpha0.35_int16_dec1_DACint4X.rbf --excess-bw 0.35 -r 4000000 --rx-gain 30 -u 1 Property changes on: gnuradio-examples/python/qpsk_fpga/commandline_rx_realtime_usrp1_rxB_dbsrx_alpha0.35_bitrate_4M_freq_900MHz.sh ___________________________________________________________________ Name: svn:executable + * Index: gnuradio-examples/python/qpsk_fpga/README.txt =================================================================== --- gnuradio-examples/python/qpsk_fpga/README.txt (revision 0) +++ gnuradio-examples/python/qpsk_fpga/README.txt (revision 0) @@ -0,0 +1,287 @@ +Quick overview of what's here: + +These are special versions of qpsk RX and TX benchmarks which use modified usrp fpga firmware with built-in RRCfilter, fractional interpolator and qpsk modulator. + +* commandline_tx_*.sh : example commandline for tx +* commandline_rx_realtime*.sh : example commandline for rx (realtime) +* commandline_rx_file*.sh : example commandline for rx (first prerecording, then demodulating) + +The python scripts which do the real work: + +* benchmark_tx_qpsk_fpga.py: generates packets of the size you +specify and sends them across the air using the USRP. +It uses special fpga firmware with built-in RRC filter, fractional interpolator and qpsk modulator. +The firmware filename has to be given on the commandline with -F firmwarefilename.rbf + +The excess-bandwidth (alpha) and interpolation factor are hardcoded in the firmware. +There are four firmwares: +The total interpolation_rate=DAC_interpolation*interpolation/decimation +the number of symbols/sec is determined by the interpolation_rate and DAC samplerate +DAC_samplerate=128 Msamples/sec +symbols_per_sec=128.0e6/interpolation_rate +bitrate=2*symbols_per_sec for qpsk +usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec10_DACint4X.rbf bitrate= 40Mbit/sec, alpha=0.2 +usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf bitrate= 4 Mbit/sec, alpha=0.2 +usrp_frac_interp_2rxhb_2tx_alpha0.35_int16_dec10_DACint4X.rbf bitrate= 40 Mbit/sec, alpha=0.35 +usrp_frac_interp_2rxhb_2tx_alpha0.35_int16_dec1_DACint4X.rbf bitrate= 4 Mbit/sec, alpha=0.35 + + +fpga_filename="usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec10_DACint4X.rbf" + +This particular example uses a firmware with +2 rx channels +2 tx channels +alpha=0.35 +interpolation=16 +decimation=1 +(so interpolation_rate=16/1=16.0) +DAC interpolation=4X +(so total interpolation=4*16=64) + +This results in a bitrate of +bits_per_symbol*DACRATE/(DAC_interpolation*(interpolation/decimation)) +=2*128000000/(4*(16/1))= 4 Mbit/sec +(qpsk has 2 bits_per_symbol) + +If you change the line with the fpga_filename to usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf +you get interpolation 4*1.6=6.4 and alpha 0.2. +So with this firmware you can send two 40 Mb/sec qpsk streams with alpha 0.2. (one on TXA and one on TXB) + +The script works well using the USRP with the RFX transceiver daughterboards or basic_TX boards. +You can not specify the bitrate. The bitrate is determined by the +fractional interpolation rate of the fpga firmware. +interpolation_rate=4*16.0 => 4 Mb/s +interpolation_rate=4*1.6 => 40 Mb/s + + +You should also pass the interpolation and decimation factor of the hardcoded fractional interpolator as commandline parameter to optimize usb throughput and to show the right bitrate + -IFI_INTERP, --fi-interp=FI_INTERP + give interpolation of fractional interpolator which is + hardcoded in selected fgpa (only used to optimise usb + transfers and calculate bitrate) [default=16] + -DFI_DECIM, --fi-decim=FI_DECIM + give decimation of fractional interpolator which is + hardcoded in selected fgpa (only used to optimise usb + transfers and calculate bitrate) [default=1] + +you should also pass the transmit RF frequency with -f or --freq + -fFREQ, --freq=FREQ set Tx and/or Rx frequency to FREQ [default=%default] + +The output level is determined by the bitshift parameter. +This reduces the output level in the digital domain before samples go to the DAC (so you do lose some resolution) + -bBITSHIFT, --bitshift=BITSHIFT + bitshift range(-15,15) determines the tx amplitude + attenuation, higher values give more attenuation, a too + low value gives overflows and/or distortion in RFX + boards 0=> +6dB 1=>0 dB (tx_amplitude=8192) 1=>-6 dB + (tx_amplitude=4096), 2=> -12 dB and so on. Values 1, 2 + and 3 are good for RFX boards [default=2] + +I added this option because RFX boards get a distortion problem when you use the full output range of the DAC. + +If you use multiple usrps you can specify which usrp to use with -u + -uUSRP, --usrp=USRP which usrp to use (0, 1, 2 ...) [default=0 is the last + one plugged in] +The last usrp plugged in is allways usrp 0, the second last is 1, the one before is 2, and so on. + +You can also select modulation type with the -m commandline argument, +but the only legal value for is dqpsk_fpga which is also the default. + + + + + +for basicTX this works well: +./benchmark_tx_qpsk_fpga.py -T A -f 16.0e6 -m dqpsk_fpga -v -F usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf -I 16 -D 1 +(see commandline_tx_txA_basicTX_alpha_0.2_bitrate_4M_freq_16MHz.sh) + +for RFX900 this should work: +./benchmark_tx_qpsk_fpga.py -T A -f 900.0e6 -v -F usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf -I 16 -D 1 +(see commandline_tx_txA_rfx900_alpha_0.2_bitrate_4M_freq_900MHz.sh) + +To show all commandline options use -h or --help + ./benchmark_tx_qpsk_fpga.py -h +usage: benchmark_tx_qpsk_fpga.py [options] + +options: + -h, --help show this help message and exit + -mMODULATION, --modulation=MODULATION + Select modulation, only dqpsk_fpga is valid for this + script [default=dqpsk_fpga] + -sSIZE, --size=SIZE set packet size [default=%default] + -MMEGABYTES, --megabytes=MEGABYTES + set megabytes to transmit [default=%default] + -fFREQ, --freq=FREQ set Tx and/or Rx frequency to FREQ [default=%default] + -uUSRP, --usrp=USRP which usrp to use (0, 1, 2 ...) [default=0 is the last + one plugged in] + -FFPGA, --fpga=FPGA set fpga_filename to FPGA [default=usrp_frac_interp_2rx + hb_2tx_alpha0.2_int16_dec1_DACint4X.rbf] + -bBITSHIFT, --bitshift=BITSHIFT + bitshift range(-15,15) determines the tx amplitude + attenuation, higher values give more attenuation, a too + low value gives overflows and/or distortion in RFX + boards 0=> +6dB 1=>0 dB (tx_amplitude=8192) 1=>-6 dB + (tx_amplitude=4096), 2=> -12 dB and so on. Values 1, 2 + and 3 are good for RFX boards [default=2] + -IFI_INTERP, --fi-interp=FI_INTERP + give interpolation of fractional interpolator which is + hardcoded in selected fgpa (only used to optimise usb + transfers and calculate bitrate) [default=16] + -DFI_DECIM, --fi-decim=FI_DECIM + give decimation of fractional interpolator which is + hardcoded in selected fgpa (only used to optimise usb + transfers and calculate bitrate) [default=1] + -TTX_SUBDEV_SPEC, --tx-subdev-spec=TX_SUBDEV_SPEC + select USRP Tx side A or B + -v, --verbose + + + + +* benchmark_rx_qpsk_fpga.py: the receiver half of benchmark_tx.py. +Command line arguments are pretty much the same as tx. +make sure you set the modulation to dqpsk with -m dqpsk +You also must set the excess-bandwidth (alpha) explicitely with --excess-bandwidth + +benchmark_rx_qpsk_fpga.py --help shows the commandline options. +Works well with a USRP and RFX transceiver daughterboards, dbs_rx or basic_rx. + +./benchmark_rx_qpsk_fpga.py -h +usage: benchmark_rx_qpsk_fpga.py [options] + +options: + -h, --help show this help message and exit + -mMODULATION, --modulation=MODULATION + Select modulation from: qam64, d8psk, qam16, dbpsk, + dqpsk, gmsk [default=%default] + -fFREQ, --freq=FREQ set Tx and/or Rx frequency to FREQ [default=%default] + -rBITRATE, --bitrate=BITRATE + specify bitrate. samples-per-symbol and interp/decim + will be derived. + -uUSRP, --usrp=USRP which usrp to use (0, 1, 2 ...) [default=0 is the last + one plugged in] + -FFPGA, --fpga=FPGA set fpga_filename to FPGA [default=usrp_frac_interp_2rx + hb_2tx_alpha0.2_int16_dec1_DACint4X.rbf] + -RRX_SUBDEV_SPEC, --rx-subdev-spec=RX_SUBDEV_SPEC + select USRP Rx side A or B + --rx-gain=GAIN set receiver gain in dB [default=midpoint]. See also + --show-rx-gain-range + --show-rx-gain-range print min and max Rx gain available on selected + daughterboard + -v, --verbose + + Expert: + -SSAMPLES_PER_SYMBOL, --samples-per-symbol=SAMPLES_PER_SYMBOL + set samples/symbol [default=%default] + -dDECIM, --decim=DECIM + set fpga decimation rate to DECIM [default=%default] + --excess-bw=EXCESS_BW + set RRC excess bandwith factor [default=%default] (PSK) + + + +example: +./benchmark_rx_qpsk_fpga.py -m dqpsk -R B -f 900.0e6 -F usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf --excess-bw 0.2 -r 4000000 --rx-gain 30 -u 0 +(see commandline_rx_realtime_usrp0_rxB_dbsrx_alpha0.2_bitrate_4M_freq_900MHz.sh) + +use usrp 0 (= the last one plugged in, in this case this is the same usrp as used for tx) +use modulation dqpsk +rf frequency 900 MHz +bitrate 4 Mbit +daughterboard B +verbose +rx-gain 30 dB +alpha 0.2 + +WHen you use seperate usrps for tx and for rx you could use: +./benchmark_rx_qpsk_fpga.py -m dqpsk -R B -f 900.0e6 -F usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf --excess-bw 0.2 -r 4000000 --rx-gain 30 -u 1 + +(see commandline_rx_realtime_usrp1_rxB_dbsrx_alpha0.2_bitrate_4M_freq_900MHz.sh) + +-u 1 use usrp 1 (=the first one plugged in, the last one plugged in is 0 which I use for transmitting in this example. + +You could even leave out the -F usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf in this case. +The receive script can use the standard firmware of the usrp. + +./benchmark_rx_qpsk_fpga.py -m dqpsk -R B -f 900.0e6 --excess-bw 0.2 -r 4000000 --rx-gain 30 -u 1 + +This only fails when you use the same usrp for both transmit and receive. In that case you have to tell the receive script to use the same firmware which is needed for the transmit side. + + +You can also work with basicRX and basicTX daughterboards. +Make sure you set the right gain (-g 10 should work) and connect both I and Q. + +Should also work with basicRX daughterboard with both I and Q connected. +Will also work with TVRX daugherboard, but you'll need to fiddle with the gain. + + + +Special notes: Since the usrp can do only 8 MSPS on receive side, +(or 16 when using 8 bit mode) you cannot receive the 40 Mb/sec which +you can send with benchmark_tx_qpsk_fpga.py when using a firmware with +interpolation_rate 1.6. +You can only receive with firmware with 16.0 interpolation_rate (4Mb/sec). +Most machines are not fast enough for this though. For this I added +benchmark_rx_qpsk_file.py + +This script can demodulate prerecorded streams. +You can record them with +usrp_rx_cfile_basicrxcomplex_fpga.py (for using basicRX daughterboard with both I and Q connected to basicTX) +or +usrp_rx_cfile_fpga.py (for recording with other daughterboards or for only using I on basicRX) + +The following examples first prerecord a stream and then demodulate it. +The recieved raw sample stream of the usrp is saved in data_cfloat.raw +commandline_rx_file_usrp0_rxA_basicRX_freq_16MHz_alpha_0.2_bitrate_4M.sh +commandline_rx_file_usrp0_rxA_basicRX_freq_16MHz_alpha_0.35_bitrate_4M.sh +commandline_rx_file_usrp0_rxB_rfx900_freq_900MHz_alpha_0.2_bitrate_4M.sh +commandline_rx_file_usrp0_rxB_rfx900_freq_900MHz_alpha_0.35_bitrate_4M.sh +commandline_rx_file_usrp1_rxB_rfx900_freq_900MHz_alpha_0.2_bitrate_4M.sh +commandline_rx_file_usrp1_rxB_rfx900_freq_900MHz_alpha_0.35_bitrate_4M.sh + +Explanation: +use it like: +usrp_rx_cfile[_basicrxcomplex_fpga].py -R daughterboard_side -d 16 -f freq -F usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf -g gain -N numberofsamplestoget data_cfloat.raw + +daughterboard_side should be A or B +f is the frequency in Hertz +gain is in decibels (use 10 for basicRX, use 30 for dbsRX) + +If you try to prerecord a stream which is send with the same usrp at the same time then +you must give the fpga firmware filename on the commandline with -F fpga_filename.rbf + +(Otherwise the usrp_rx_cfile_XXX_fpga.py script tries to load the + default firmware while the benchmark_tx_qpsk_fpga.py has loaded the + qpsk firmware, which will halt both scripts) + +Now you can demodulate the stream with usrp_rx_cfile_complex_fpga.py +The default filename of the prerecorded stream is data_cfloat.raw + +benchmark_rx_qpsk_file.py -m dqpsk -F data_cfloat.raw -f 0.0 -r 4000000 -v -S 2 -d 16 --excess-bw=0.35 + +./benchmark_rx_qpsk_file.py -h +usage: benchmark_rx_qpsk_file.py [options] + +options: + -h, --help show this help message and exit + -mMODULATION, --modulation=MODULATION + Select modulation from: qam64, d8psk, qam16, dbpsk, + dqpsk, gmsk [default=%default] + -FFILENAME, --filename=FILENAME + filename + -fFREQ, --freq=FREQ set Tx and/or Rx frequency to FREQ [default=%default] + -rBITRATE, --bitrate=BITRATE + specify bitrate. samples-per-symbol and interp/decim + will be derived. + -v, --verbose + + Expert: + -SSAMPLES_PER_SYMBOL, --samples-per-symbol=SAMPLES_PER_SYMBOL + set samples/symbol [default=%default] + --excess-bw=EXCESS_BW + set RRC excess bandwith factor [default=%default] (PSK) + + + + + Index: gnuradio-examples/python/qpsk_fpga/commandline_rx_file_usrp0_rxA_basicRX_freq_16MHz_alpha_0.35_bitrate_4M.sh =================================================================== --- gnuradio-examples/python/qpsk_fpga/commandline_rx_file_usrp0_rxA_basicRX_freq_16MHz_alpha_0.35_bitrate_4M.sh (revision 0) +++ gnuradio-examples/python/qpsk_fpga/commandline_rx_file_usrp0_rxA_basicRX_freq_16MHz_alpha_0.35_bitrate_4M.sh (revision 0) @@ -0,0 +1,4 @@ +#!/bin/sh +./usrp_rx_cfile_basicrxcomplex_fpga.py -u 0 -R A -d 16 -f 16.0e6 -F usrp_frac_interp_2rxhb_2tx_alpha0.35_int16_dec1_DACint4X.rbf -g 10 -N 10000000 data_cfloat.raw +./benchmark_rx_qpsk_file.py -m dqpsk -d 16 -f 0 -S 2 -r 40000000 -v --excess-bw=0.35 + Property changes on: gnuradio-examples/python/qpsk_fpga/commandline_rx_file_usrp0_rxA_basicRX_freq_16MHz_alpha_0.35_bitrate_4M.sh ___________________________________________________________________ Name: svn:executable + * Index: usrp/fpga/Makefile.extra =================================================================== --- usrp/fpga/Makefile.extra (revision 6827) +++ usrp/fpga/Makefile.extra (working copy) @@ -103,7 +103,19 @@ sdr_lib/strobe_gen.v \ sdr_lib/tx_buffer.v \ sdr_lib/tx_chain.v \ - sdr_lib/tx_chain_hb.v \ + sdr_lib/tx_chain_0.v \ + sdr_lib/tx_chain_1.v \ + sdr_lib/tx_chain_hb.v \ + sdr_lib/frac_interp_0.v \ + sdr_lib/frac_interp_1.v \ + sdr_lib/frac_interp_alpha0.2_int16_dec10_DACint4X_chan0.v \ + sdr_lib/frac_interp_alpha0.2_int16_dec10_DACint4X_chan1.v \ + sdr_lib/frac_interp_alpha0.2_int16_dec1_DACint4X_chan0.v \ + sdr_lib/frac_interp_alpha0.2_int16_dec1_DACint4X_chan1.v \ + sdr_lib/frac_interp_alpha0.35_int16_dec10_DACint4X_chan0.v \ + sdr_lib/frac_interp_alpha0.35_int16_dec10_DACint4X_chan1.v \ + sdr_lib/frac_interp_alpha0.35_int16_dec1_DACint4X_chan0.v \ + sdr_lib/frac_interp_alpha0.35_int16_dec1_DACint4X_chan1.v \ tb/cbus_tb.v \ tb/cordic_tb.v \ tb/decim_tb.v \ @@ -147,5 +159,6 @@ toplevel/usrp_std/usrp_std.qsf \ toplevel/usrp_std/usrp_std.v \ toplevel/usrp_std/usrp_std.vh \ + toplevel/usrp_std/usrp_std_config_2rxhb_1tx.vh \ toplevel/usrp_std/usrp_std_config_2rxhb_2tx.vh \ toplevel/usrp_std/usrp_std_config_4rx_0tx.vh Index: usrp/fpga/rbf/rev4/usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec10_DACint4X.rbf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Property changes on: usrp/fpga/rbf/rev4/usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec10_DACint4X.rbf ___________________________________________________________________ Name: svn:executable + * Name: svn:mime-type + application/octet-stream Index: usrp/fpga/rbf/rev4/usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Property changes on: usrp/fpga/rbf/rev4/usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf ___________________________________________________________________ Name: svn:executable + * Name: svn:mime-type + application/octet-stream Index: usrp/fpga/rbf/rev4/usrp_frac_interp_2rxhb_2tx_alpha0.35_int16_dec10_DACint4X.rbf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Property changes on: usrp/fpga/rbf/rev4/usrp_frac_interp_2rxhb_2tx_alpha0.35_int16_dec10_DACint4X.rbf ___________________________________________________________________ Name: svn:executable + * Name: svn:mime-type + application/octet-stream Index: usrp/fpga/rbf/rev4/usrp_frac_interp_2rxhb_2tx_alpha0.35_int16_dec1_DACint4X.rbf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Property changes on: usrp/fpga/rbf/rev4/usrp_frac_interp_2rxhb_2tx_alpha0.35_int16_dec1_DACint4X.rbf ___________________________________________________________________ Name: svn:executable + * Name: svn:mime-type + application/octet-stream Index: usrp/fpga/rbf/Makefile.am =================================================================== --- usrp/fpga/rbf/Makefile.am (revision 6827) +++ usrp/fpga/rbf/Makefile.am (working copy) @@ -24,6 +24,14 @@ datadir = $(prefix)/share/usrp rbfs = \ + rev2/usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf \ + rev4/usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf \ + rev2/usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec10_DACint4X.rbf \ + rev4/usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec10_DACint4X.rbf \ + rev2/usrp_frac_interp_2rxhb_2tx_alpha0.35_int16_dec1_DACint4X.rbf \ + rev4/usrp_frac_interp_2rxhb_2tx_alpha0.35_int16_dec1_DACint4X.rbf \ + rev2/usrp_frac_interp_2rxhb_2tx_alpha0.35_int16_dec10_DACint4X.rbf \ + rev4/usrp_frac_interp_2rxhb_2tx_alpha0.35_int16_dec10_DACint4X.rbf \ rev2/std_2rxhb_2tx.rbf \ rev2/std_4rx_0tx.rbf \ rev4/std_2rxhb_2tx.rbf \ Index: usrp/fpga/rbf/rev2/usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec10_DACint4X.rbf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Property changes on: usrp/fpga/rbf/rev2/usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec10_DACint4X.rbf ___________________________________________________________________ Name: svn:executable + * Name: svn:mime-type + application/octet-stream Index: usrp/fpga/rbf/rev2/usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Property changes on: usrp/fpga/rbf/rev2/usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf ___________________________________________________________________ Name: svn:executable + * Name: svn:mime-type + application/octet-stream Index: usrp/fpga/rbf/rev2/usrp_frac_interp_2rxhb_2tx_alpha0.35_int16_dec10_DACint4X.rbf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Property changes on: usrp/fpga/rbf/rev2/usrp_frac_interp_2rxhb_2tx_alpha0.35_int16_dec10_DACint4X.rbf ___________________________________________________________________ Name: svn:executable + * Name: svn:mime-type + application/octet-stream Index: usrp/fpga/rbf/rev2/usrp_frac_interp_2rxhb_2tx_alpha0.35_int16_dec1_DACint4X.rbf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Property changes on: usrp/fpga/rbf/rev2/usrp_frac_interp_2rxhb_2tx_alpha0.35_int16_dec1_DACint4X.rbf ___________________________________________________________________ Name: svn:executable + * Name: svn:mime-type + application/octet-stream Index: usrp/fpga/toplevel/usrp_std/usrp_std_config_2rxhb_1tx.vh =================================================================== --- usrp/fpga/toplevel/usrp_std/usrp_std_config_2rxhb_1tx.vh (revision 0) +++ usrp/fpga/toplevel/usrp_std/usrp_std_config_2rxhb_1tx.vh (revision 0) @@ -0,0 +1,61 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2006 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +// ------------------------------------------------------------ +// If TX_ON is not defined, there is *no* transmit circuitry built + `define TX_ON + +// ------------------------------------------------------------ +// Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD +// to respectively enable 1, 2 or 4 transmit channels. +// [Please note that only TX_DUAL is currently valid] +`define TX_SINGLE +//`define TX_DUAL +//`define TX_QUAD + +// ------------------------------------------------------------ +// Define TX_HB_ON to enable the transmit halfband filter +// [Not implemented] +//`define TX_HB_ON + +// ------------------------------------------------------------ +// IF RX_ON is not defined, there is *no* transmit circuitry built + `define RX_ON + +// ------------------------------------------------------------ +// Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD +// to respectively define 1, 2 or 4 receive channels. + +//`define RX_SINGLE + `define RX_DUAL +//`define RX_QUAD + +// ------------------------------------------------------------ +// Define RX_HB_ON to enable the receive halfband filter + `define RX_HB_ON + +// ------------------------------------------------------------ +// Define RX_NCO_ON to enable the receive Numerical Controlled Osc + `define RX_NCO_ON + +// ------------------------------------------------------------ +// Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter + `define RX_CIC_ON Index: usrp/fpga/toplevel/usrp_std/usrp_std.v =================================================================== --- usrp/fpga/toplevel/usrp_std/usrp_std.v (revision 6827) +++ usrp/fpga/toplevel/usrp_std/usrp_std.v (working copy) @@ -142,17 +142,28 @@ .tx_empty(tx_empty), .debugbus(tx_debugbus) ); - tx_chain tx_chain_0 +`ifdef TX_EN_0 + tx_chain_0 #(`FR_USER_1) tx_chain_0 ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx), .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe), .interpolator_strobe(strobe_interp),.freq(), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), .i_in(bb_tx_i0),.q_in(bb_tx_q0),.i_out(i_out_0),.q_out(q_out_0) ); +`else + assign i_out_0=16'd0; + assign q_out_0=16'd0; +`endif // `ifdef TX_EN_0 - tx_chain tx_chain_1 +`ifdef TX_EN_1 + tx_chain_1 tx_chain_1 ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx), .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe), - .interpolator_strobe(strobe_interp),.freq(), + .interpolator_strobe(),.freq(), .i_in(bb_tx_i1),.q_in(bb_tx_q1),.i_out(i_out_1),.q_out(q_out_1) ); +`else + assign i_out_1=16'd0; + assign q_out_1=16'd0; +`endif // `ifdef TX_EN_1 setting_reg #(`FR_TX_MUX) sr_txmux(.clock(clk64),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data), @@ -303,7 +314,7 @@ .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset), .enable_tx(enable_tx),.enable_rx(enable_rx), .interp_rate(interp_rate),.decim_rate(decim_rate), - .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp), + .tx_sample_strobe(tx_sample_strobe),.strobe_interp(),//.strobe_interp(strobe_interp), .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim), .tx_empty(tx_empty), //.debug_0(rx_a_a),.debug_1(ddc0_in_i), Index: usrp/fpga/sdr_lib/frac_interp_alpha0.35_int16_dec10_DACint4X_chan0.v =================================================================== --- usrp/fpga/sdr_lib/frac_interp_alpha0.35_int16_dec10_DACint4X_chan0.v (revision 0) +++ usrp/fpga/sdr_lib/frac_interp_alpha0.35_int16_dec10_DACint4X_chan0.v (revision 0) @@ -0,0 +1,879 @@ +// -*- verilog -*- +// +// Polyphase interpolating Root-Raised-Cosine filter +// +// Copyright (C) 2007 Martin Dudok van Heel +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// +// Polyphase interpolating Root-Raised-Cosine filter +// Interpolation ratio can be fractional (float) +// +// This file was generated by ./generate_frac_interp_05nov2007.py at 2007-11-08 00:15:22.294603 +// Written by Martin Dudok van Heel, 2007 +// Olifantasia +// +// Contact: http://www.olifantasia.com/gnuradio/contact.gif or nldudok1_olifantasia_com +// http://www.olifantasia.com +// +// This file can be used to build a special purpose firmware for the USRP +// USRP = Universal Software Radio Peripheral +// This special purpose firmware in combination with the GnuRadio framework can be used to create a high speed QPSK transmitter +// Depending on the decimation and interpolation factors used, the symbolrate can be from 2 to 20 Msymbols/sec +// The corresponding QPSK bitrate is 4 to 40 Mbit/sec +// alpha= 0.35 +// interpolation = 16.0 decimation= 10.0 interp_ratio= 1.6 decim_ratio= 0.625 +// symbol rate = 20.0 Msymbol/sec +// QPSK bitrate = 40.0 Mbit/sec +// +//fractional ntaps 17.6 +//ntaps_per_filter= 11 +//nfilters= 16 +// s f incr d_mu ii oo step +// 0.0 0.0 0 0.0 0 0 0 +// 0.625 0.0 0 0.625 0 1 1 +// 1.25 1.0 1 0.25 1 2 2 +// 0.875 0.0 0 0.875 1 3 3 +// 1.5 1.0 1 0.5 2 4 4 +// 1.125 1.0 1 0.125 3 5 5 +// 0.75 0.0 0 0.75 3 6 6 +// 1.375 1.0 1 0.375 4 7 7 +// 1.0 1.0 1 0.0 5 8 8 +// 0.625 0.0 0 0.625 5 9 9 +// 1.25 1.0 1 0.25 6 10 10 +// 0.875 0.0 0 0.875 6 11 11 +// 1.5 1.0 1 0.5 7 12 12 +// 1.125 1.0 1 0.125 8 13 13 +// 0.75 0.0 0 0.75 8 14 14 +// 1.375 1.0 1 0.375 9 15 15 +//poly_filter[ 0 ] = +// [0.0075129163196754143, 0.0020458085258023588, -0.025488551496836223, 0.057197572717172032, -0.084806311229650128, 1.0971351131785818, -0.084806311229650128, 0.057197572717172032, -0.025488551496836223, 0.0020458085258023588, 0.0075129163196754143] + +//poly_filter[ 1 ] = +// [-0.0013039776546781791, -0.0078269741673739467, 0.013835225353669441, 0.002852740888603599, -0.079417311797210149, 0.40311908078699055, 0.80118104720156236, -0.17646842387834014, 0.048603951449408038, 0.0011463481286299721, -0.01263496157797927] + +//poly_filter[ 2 ] = +// [0.0092022137140799678, -0.010284732153928977, -0.0095621618982352288, 0.065433931294967412, -0.18889153520490076, 0.95843746473199454, 0.20715466856520273, -0.022102879562705985, -0.014795407502031947, 0.013338514291149838, -0.0023810270307585914] + +//poly_filter[ 3 ] = +// [-0.0061008521195972838, 0.0031972964531200854, 0.0088445847910837132, -0.024414733630969649, 0.025733284007473971, 0.03998468989127623, 1.0613394960075577, -0.16078491709665643, 0.069870145274482917, -0.019566539655389181, -0.0049678758232720738] + +//poly_filter[ 4 ] = +// [0.0027539244869444345, -0.011642548473894643, 0.009585493131322181, 0.025650092551220097, -0.13534932275453265, 0.60860640890431328, 0.60860640890431328, -0.13534932275453265, 0.025650092551220097, 0.009585493131322181, -0.011642548473894643] + +//poly_filter[ 5 ] = +// [0.0096164209789455068, -0.0049678758232720738, -0.019566539655389181, 0.069870145274482917, -0.16078491709665643, 1.0613394960075577, 0.03998468989127623, 0.025733284007473971, -0.024414733630969649, 0.0088445847910837132, 0.0031972964531200854] + +//poly_filter[ 6 ] = +// [-0.0044979561915869572, -0.0023810270307585914, 0.013338514291149838, -0.014795407502031947, -0.022102879562705985, 0.20715466856520273, 0.95843746473199454, -0.18889153520490076, 0.065433931294967412, -0.0095621618982352288, -0.010284732153928977] + +//poly_filter[ 7 ] = +// [0.0066260209432802133, -0.01263496157797927, 0.0011463481286299721, 0.048603951449408038, -0.17646842387834014, 0.80118104720156236, 0.40311908078699055, -0.079417311797210149, 0.002852740888603599, 0.013835225353669441, -0.0078269741673739467] + +//poly_filter[ 8 ] = +// [0.0075129163196754143, 0.0020458085258023588, -0.025488551496836223, 0.057197572717172032, -0.084806311229650128, 1.0971351131785818, -0.084806311229650128, 0.057197572717172032, -0.025488551496836223, 0.0020458085258023588, 0.0075129163196754143] + +//poly_filter[ 9 ] = +// [-0.0013039776546781791, -0.0078269741673739467, 0.013835225353669441, 0.002852740888603599, -0.079417311797210149, 0.40311908078699055, 0.80118104720156236, -0.17646842387834014, 0.048603951449408038, 0.0011463481286299721, -0.01263496157797927] + +//poly_filter[ 10 ] = +// [0.0092022137140799678, -0.010284732153928977, -0.0095621618982352288, 0.065433931294967412, -0.18889153520490076, 0.95843746473199454, 0.20715466856520273, -0.022102879562705985, -0.014795407502031947, 0.013338514291149838, -0.0023810270307585914] + +//poly_filter[ 11 ] = +// [-0.0061008521195972838, 0.0031972964531200854, 0.0088445847910837132, -0.024414733630969649, 0.025733284007473971, 0.03998468989127623, 1.0613394960075577, -0.16078491709665643, 0.069870145274482917, -0.019566539655389181, -0.0049678758232720738] + +//poly_filter[ 12 ] = +// [0.0027539244869444345, -0.011642548473894643, 0.009585493131322181, 0.025650092551220097, -0.13534932275453265, 0.60860640890431328, 0.60860640890431328, -0.13534932275453265, 0.025650092551220097, 0.009585493131322181, -0.011642548473894643] + +//poly_filter[ 13 ] = +// [0.0096164209789455068, -0.0049678758232720738, -0.019566539655389181, 0.069870145274482917, -0.16078491709665643, 1.0613394960075577, 0.03998468989127623, 0.025733284007473971, -0.024414733630969649, 0.0088445847910837132, 0.0031972964531200854] + +//poly_filter[ 14 ] = +// [-0.0044979561915869572, -0.0023810270307585914, 0.013338514291149838, -0.014795407502031947, -0.022102879562705985, 0.20715466856520273, 0.95843746473199454, -0.18889153520490076, 0.065433931294967412, -0.0095621618982352288, -0.010284732153928977] + +//poly_filter[ 15 ] = +// [0.0066260209432802133, -0.01263496157797927, 0.0011463481286299721, 0.048603951449408038, -0.17646842387834014, 0.80118104720156236, 0.40311908078699055, -0.079417311797210149, 0.002852740888603599, 0.013835225353669441, -0.0078269741673739467] + +// total_ntaps= 176 +// ntaps_per_filter= 11 +// nfilters= 16 +// filter resolution= 16 bits +// +//data_size= 5 phase_size= 4 +//abs_max= 1.43051885144 abs_max_16bit= 32767 signed_max_16bit= 32743 signed_min_16bit= -32767 +//nmemories= 3 +//incr_list = [1, 3, 4, 6, 7, 9, 11, 12, 14, 15] +//bw= 14 data_size= 5 abs_max= 6491 len= 16 +module rrc_coeff_ram_generated0_0 (input clock, input strobe, input [3:0] phase, input [4:0] in_data, output [13:0] out_data,output [17:0] ext_out_data); + +reg reg_quadrant; +wire quadrant=in_data[4]; +wire [7:0] rd_addr={phase,quadrant?~in_data[3:0]:in_data[3:0]}; +reg [13:0] rd_data; + + always @(posedge clock) + if (strobe) + begin + reg_quadrant <= #1 quadrant; + case (rd_addr) + 8'd0 : rd_data <= #1 14'd997; + 8'd1 : rd_data <= #1 14'd1341; + 8'd2 : rd_data <= #1 14'd1091; + 8'd3 : rd_data <= #1 14'd1435; + 8'd4 : rd_data <= #1 -14'd170; + 8'd5 : rd_data <= #1 14'd174; + 8'd6 : rd_data <= #1 -14'd77; + 8'd7 : rd_data <= #1 14'd268; + 8'd8 : rd_data <= #1 14'd3618; + 8'd9 : rd_data <= #1 14'd3962; + 8'd10 : rd_data <= #1 14'd3711; + 8'd11 : rd_data <= #1 14'd4055; + 8'd12 : rd_data <= #1 14'd2450; + 8'd13 : rd_data <= #1 14'd2794; + 8'd14 : rd_data <= #1 14'd2544; + 8'd15 : rd_data <= #1 14'd2888; + 8'd16 : rd_data <= #1 14'd1646; + 8'd17 : rd_data <= #1 14'd1586; + 8'd18 : rd_data <= #1 14'd1287; + 8'd19 : rd_data <= #1 14'd1228; + 8'd20 : rd_data <= #1 14'd2280; + 8'd21 : rd_data <= #1 14'd2220; + 8'd22 : rd_data <= #1 14'd1921; + 8'd23 : rd_data <= #1 14'd1862; + 8'd24 : rd_data <= #1 14'd1777; + 8'd25 : rd_data <= #1 14'd1717; + 8'd26 : rd_data <= #1 14'd1418; + 8'd27 : rd_data <= #1 14'd1358; + 8'd28 : rd_data <= #1 14'd2411; + 8'd29 : rd_data <= #1 14'd2351; + 8'd30 : rd_data <= #1 14'd2052; + 8'd31 : rd_data <= #1 14'd1992; + 8'd32 : rd_data <= #1 14'd3072; + 8'd33 : rd_data <= #1 14'd3493; + 8'd34 : rd_data <= #1 14'd2601; + 8'd35 : rd_data <= #1 14'd3022; + 8'd36 : rd_data <= #1 14'd2634; + 8'd37 : rd_data <= #1 14'd3055; + 8'd38 : rd_data <= #1 14'd2162; + 8'd39 : rd_data <= #1 14'd2584; + 8'd40 : rd_data <= #1 14'd6069; + 8'd41 : rd_data <= #1 14'd6491; + 8'd42 : rd_data <= #1 14'd5598; + 8'd43 : rd_data <= #1 14'd6020; + 8'd44 : rd_data <= #1 14'd5631; + 8'd45 : rd_data <= #1 14'd6053; + 8'd46 : rd_data <= #1 14'd5160; + 8'd47 : rd_data <= #1 14'd5582; + 8'd48 : rd_data <= #1 -14'd166; + 8'd49 : rd_data <= #1 -14'd446; + 8'd50 : rd_data <= #1 -14'd20; + 8'd51 : rd_data <= #1 -14'd299; + 8'd52 : rd_data <= #1 14'd239; + 8'd53 : rd_data <= #1 -14'd41; + 8'd54 : rd_data <= #1 14'd385; + 8'd55 : rd_data <= #1 14'd106; + 8'd56 : rd_data <= #1 -14'd1285; + 8'd57 : rd_data <= #1 -14'd1564; + 8'd58 : rd_data <= #1 -14'd1138; + 8'd59 : rd_data <= #1 -14'd1418; + 8'd60 : rd_data <= #1 -14'd880; + 8'd61 : rd_data <= #1 -14'd1159; + 8'd62 : rd_data <= #1 -14'd733; + 8'd63 : rd_data <= #1 -14'd1013; + 8'd64 : rd_data <= #1 14'd2497; + 8'd65 : rd_data <= #1 14'd2623; + 8'd66 : rd_data <= #1 14'd1963; + 8'd67 : rd_data <= #1 14'd2090; + 8'd68 : rd_data <= #1 14'd2936; + 8'd69 : rd_data <= #1 14'd3062; + 8'd70 : rd_data <= #1 14'd2403; + 8'd71 : rd_data <= #1 14'd2529; + 8'd72 : rd_data <= #1 14'd3672; + 8'd73 : rd_data <= #1 14'd3798; + 8'd74 : rd_data <= #1 14'd3138; + 8'd75 : rd_data <= #1 14'd3265; + 8'd76 : rd_data <= #1 14'd4111; + 8'd77 : rd_data <= #1 14'd4237; + 8'd78 : rd_data <= #1 14'd3578; + 8'd79 : rd_data <= #1 14'd3704; + 8'd80 : rd_data <= #1 14'd2424; + 8'd81 : rd_data <= #1 14'd2865; + 8'd82 : rd_data <= #1 14'd2197; + 8'd83 : rd_data <= #1 14'd2637; + 8'd84 : rd_data <= #1 14'd1528; + 8'd85 : rd_data <= #1 14'd1968; + 8'd86 : rd_data <= #1 14'd1300; + 8'd87 : rd_data <= #1 14'd1741; + 8'd88 : rd_data <= #1 14'd5625; + 8'd89 : rd_data <= #1 14'd6066; + 8'd90 : rd_data <= #1 14'd5397; + 8'd91 : rd_data <= #1 14'd5838; + 8'd92 : rd_data <= #1 14'd4729; + 8'd93 : rd_data <= #1 14'd5169; + 8'd94 : rd_data <= #1 14'd4501; + 8'd95 : rd_data <= #1 14'd4942; + 8'd96 : rd_data <= #1 14'd697; + 8'd97 : rd_data <= #1 14'd491; + 8'd98 : rd_data <= #1 14'd588; + 8'd99 : rd_data <= #1 14'd382; + 8'd100 : rd_data <= #1 14'd1308; + 8'd101 : rd_data <= #1 14'd1102; + 8'd102 : rd_data <= #1 14'd1199; + 8'd103 : rd_data <= #1 14'd993; + 8'd104 : rd_data <= #1 14'd19; + 8'd105 : rd_data <= #1 -14'd187; + 8'd106 : rd_data <= #1 -14'd90; + 8'd107 : rd_data <= #1 -14'd296; + 8'd108 : rd_data <= #1 14'd630; + 8'd109 : rd_data <= #1 14'd424; + 8'd110 : rd_data <= #1 14'd521; + 8'd111 : rd_data <= #1 14'd315; + 8'd112 : rd_data <= #1 14'd3040; + 8'd113 : rd_data <= #1 14'd3344; + 8'd114 : rd_data <= #1 14'd2461; + 8'd115 : rd_data <= #1 14'd2765; + 8'd116 : rd_data <= #1 14'd3093; + 8'd117 : rd_data <= #1 14'd3396; + 8'd118 : rd_data <= #1 14'd2514; + 8'd119 : rd_data <= #1 14'd2817; + 8'd120 : rd_data <= #1 14'd5267; + 8'd121 : rd_data <= #1 14'd5570; + 8'd122 : rd_data <= #1 14'd4688; + 8'd123 : rd_data <= #1 14'd4992; + 8'd124 : rd_data <= #1 14'd5319; + 8'd125 : rd_data <= #1 14'd5623; + 8'd126 : rd_data <= #1 14'd4741; + 8'd127 : rd_data <= #1 14'd5044; + 8'd128 : rd_data <= #1 14'd997; + 8'd129 : rd_data <= #1 14'd1341; + 8'd130 : rd_data <= #1 14'd1091; + 8'd131 : rd_data <= #1 14'd1435; + 8'd132 : rd_data <= #1 -14'd170; + 8'd133 : rd_data <= #1 14'd174; + 8'd134 : rd_data <= #1 -14'd77; + 8'd135 : rd_data <= #1 14'd268; + 8'd136 : rd_data <= #1 14'd3618; + 8'd137 : rd_data <= #1 14'd3962; + 8'd138 : rd_data <= #1 14'd3711; + 8'd139 : rd_data <= #1 14'd4055; + 8'd140 : rd_data <= #1 14'd2450; + 8'd141 : rd_data <= #1 14'd2794; + 8'd142 : rd_data <= #1 14'd2544; + 8'd143 : rd_data <= #1 14'd2888; + 8'd144 : rd_data <= #1 14'd1646; + 8'd145 : rd_data <= #1 14'd1586; + 8'd146 : rd_data <= #1 14'd1287; + 8'd147 : rd_data <= #1 14'd1228; + 8'd148 : rd_data <= #1 14'd2280; + 8'd149 : rd_data <= #1 14'd2220; + 8'd150 : rd_data <= #1 14'd1921; + 8'd151 : rd_data <= #1 14'd1862; + 8'd152 : rd_data <= #1 14'd1777; + 8'd153 : rd_data <= #1 14'd1717; + 8'd154 : rd_data <= #1 14'd1418; + 8'd155 : rd_data <= #1 14'd1358; + 8'd156 : rd_data <= #1 14'd2411; + 8'd157 : rd_data <= #1 14'd2351; + 8'd158 : rd_data <= #1 14'd2052; + 8'd159 : rd_data <= #1 14'd1992; + 8'd160 : rd_data <= #1 14'd3072; + 8'd161 : rd_data <= #1 14'd3493; + 8'd162 : rd_data <= #1 14'd2601; + 8'd163 : rd_data <= #1 14'd3022; + 8'd164 : rd_data <= #1 14'd2634; + 8'd165 : rd_data <= #1 14'd3055; + 8'd166 : rd_data <= #1 14'd2162; + 8'd167 : rd_data <= #1 14'd2584; + 8'd168 : rd_data <= #1 14'd6069; + 8'd169 : rd_data <= #1 14'd6491; + 8'd170 : rd_data <= #1 14'd5598; + 8'd171 : rd_data <= #1 14'd6020; + 8'd172 : rd_data <= #1 14'd5631; + 8'd173 : rd_data <= #1 14'd6053; + 8'd174 : rd_data <= #1 14'd5160; + 8'd175 : rd_data <= #1 14'd5582; + 8'd176 : rd_data <= #1 -14'd166; + 8'd177 : rd_data <= #1 -14'd446; + 8'd178 : rd_data <= #1 -14'd20; + 8'd179 : rd_data <= #1 -14'd299; + 8'd180 : rd_data <= #1 14'd239; + 8'd181 : rd_data <= #1 -14'd41; + 8'd182 : rd_data <= #1 14'd385; + 8'd183 : rd_data <= #1 14'd106; + 8'd184 : rd_data <= #1 -14'd1285; + 8'd185 : rd_data <= #1 -14'd1564; + 8'd186 : rd_data <= #1 -14'd1138; + 8'd187 : rd_data <= #1 -14'd1418; + 8'd188 : rd_data <= #1 -14'd880; + 8'd189 : rd_data <= #1 -14'd1159; + 8'd190 : rd_data <= #1 -14'd733; + 8'd191 : rd_data <= #1 -14'd1013; + 8'd192 : rd_data <= #1 14'd2497; + 8'd193 : rd_data <= #1 14'd2623; + 8'd194 : rd_data <= #1 14'd1963; + 8'd195 : rd_data <= #1 14'd2090; + 8'd196 : rd_data <= #1 14'd2936; + 8'd197 : rd_data <= #1 14'd3062; + 8'd198 : rd_data <= #1 14'd2403; + 8'd199 : rd_data <= #1 14'd2529; + 8'd200 : rd_data <= #1 14'd3672; + 8'd201 : rd_data <= #1 14'd3798; + 8'd202 : rd_data <= #1 14'd3138; + 8'd203 : rd_data <= #1 14'd3265; + 8'd204 : rd_data <= #1 14'd4111; + 8'd205 : rd_data <= #1 14'd4237; + 8'd206 : rd_data <= #1 14'd3578; + 8'd207 : rd_data <= #1 14'd3704; + 8'd208 : rd_data <= #1 14'd2424; + 8'd209 : rd_data <= #1 14'd2865; + 8'd210 : rd_data <= #1 14'd2197; + 8'd211 : rd_data <= #1 14'd2637; + 8'd212 : rd_data <= #1 14'd1528; + 8'd213 : rd_data <= #1 14'd1968; + 8'd214 : rd_data <= #1 14'd1300; + 8'd215 : rd_data <= #1 14'd1741; + 8'd216 : rd_data <= #1 14'd5625; + 8'd217 : rd_data <= #1 14'd6066; + 8'd218 : rd_data <= #1 14'd5397; + 8'd219 : rd_data <= #1 14'd5838; + 8'd220 : rd_data <= #1 14'd4729; + 8'd221 : rd_data <= #1 14'd5169; + 8'd222 : rd_data <= #1 14'd4501; + 8'd223 : rd_data <= #1 14'd4942; + 8'd224 : rd_data <= #1 14'd697; + 8'd225 : rd_data <= #1 14'd491; + 8'd226 : rd_data <= #1 14'd588; + 8'd227 : rd_data <= #1 14'd382; + 8'd228 : rd_data <= #1 14'd1308; + 8'd229 : rd_data <= #1 14'd1102; + 8'd230 : rd_data <= #1 14'd1199; + 8'd231 : rd_data <= #1 14'd993; + 8'd232 : rd_data <= #1 14'd19; + 8'd233 : rd_data <= #1 -14'd187; + 8'd234 : rd_data <= #1 -14'd90; + 8'd235 : rd_data <= #1 -14'd296; + 8'd236 : rd_data <= #1 14'd630; + 8'd237 : rd_data <= #1 14'd424; + 8'd238 : rd_data <= #1 14'd521; + 8'd239 : rd_data <= #1 14'd315; + 8'd240 : rd_data <= #1 14'd3040; + 8'd241 : rd_data <= #1 14'd3344; + 8'd242 : rd_data <= #1 14'd2461; + 8'd243 : rd_data <= #1 14'd2765; + 8'd244 : rd_data <= #1 14'd3093; + 8'd245 : rd_data <= #1 14'd3396; + 8'd246 : rd_data <= #1 14'd2514; + 8'd247 : rd_data <= #1 14'd2817; + 8'd248 : rd_data <= #1 14'd5267; + 8'd249 : rd_data <= #1 14'd5570; + 8'd250 : rd_data <= #1 14'd4688; + 8'd251 : rd_data <= #1 14'd4992; + 8'd252 : rd_data <= #1 14'd5319; + 8'd253 : rd_data <= #1 14'd5623; + 8'd254 : rd_data <= #1 14'd4741; + 8'd255 : rd_data <= #1 14'd5044; + endcase // case(rd_addr) + end //if (strobe) + assign out_data[13:0]=reg_quadrant?-rd_data:rd_data; + sign_extend #(14,18) + ext_output (.in(out_data),.out(ext_out_data)); + +endmodule // rrc_coeff_ram_generated_0 + +//bw= 16 data_size= 5 abs_max= 32767 len= 16 +module rrc_coeff_ram_generated0_1 (input clock, input strobe, input [3:0] phase, input [4:0] in_data, output [15:0] out_data,output [17:0] ext_out_data); + +reg reg_quadrant; +wire quadrant=in_data[4]; +wire [7:0] rd_addr={phase,quadrant?~in_data[3:0]:in_data[3:0]}; +reg [15:0] rd_data; + + always @(posedge clock) + if (strobe) + begin + reg_quadrant <= #1 quadrant; + case (rd_addr) + 8'd0 : rd_data <= #1 -16'd23961; + 8'd1 : rd_data <= #1 16'd26300; + 8'd2 : rd_data <= #1 -16'd27846; + 8'd3 : rd_data <= #1 16'd22415; + 8'd4 : rd_data <= #1 -16'd21341; + 8'd5 : rd_data <= #1 16'd28920; + 8'd6 : rd_data <= #1 -16'd25226; + 8'd7 : rd_data <= #1 16'd25035; + 8'd8 : rd_data <= #1 -16'd25129; + 8'd9 : rd_data <= #1 16'd25132; + 8'd10 : rd_data <= #1 -16'd29014; + 8'd11 : rd_data <= #1 16'd21247; + 8'd12 : rd_data <= #1 -16'd22509; + 8'd13 : rd_data <= #1 16'd27753; + 8'd14 : rd_data <= #1 -16'd26394; + 8'd15 : rd_data <= #1 16'd23868; + 8'd16 : rd_data <= #1 -16'd24683; + 8'd17 : rd_data <= #1 -16'd6215; + 8'd18 : rd_data <= #1 16'd12020; + 8'd19 : rd_data <= #1 16'd30488; + 8'd20 : rd_data <= #1 -16'd32767; + 8'd21 : rd_data <= #1 -16'd14300; + 8'd22 : rd_data <= #1 16'd3936; + 8'd23 : rd_data <= #1 16'd22404; + 8'd24 : rd_data <= #1 -16'd22456; + 8'd25 : rd_data <= #1 -16'd3989; + 8'd26 : rd_data <= #1 16'd14247; + 8'd27 : rd_data <= #1 16'd32714; + 8'd28 : rd_data <= #1 -16'd30540; + 8'd29 : rd_data <= #1 -16'd12073; + 8'd30 : rd_data <= #1 16'd6163; + 8'd31 : rd_data <= #1 16'd24630; + 8'd32 : rd_data <= #1 -16'd26159; + 8'd33 : rd_data <= #1 16'd17748; + 8'd34 : rd_data <= #1 -16'd16669; + 8'd35 : rd_data <= #1 16'd27238; + 8'd36 : rd_data <= #1 -16'd27172; + 8'd37 : rd_data <= #1 16'd16736; + 8'd38 : rd_data <= #1 -16'd17682; + 8'd39 : rd_data <= #1 16'd26226; + 8'd40 : rd_data <= #1 -16'd26837; + 8'd41 : rd_data <= #1 16'd17070; + 8'd42 : rd_data <= #1 -16'd17347; + 8'd43 : rd_data <= #1 16'd26561; + 8'd44 : rd_data <= #1 -16'd27849; + 8'd45 : rd_data <= #1 16'd16058; + 8'd46 : rd_data <= #1 -16'd18359; + 8'd47 : rd_data <= #1 16'd25548; + 8'd48 : rd_data <= #1 -16'd22696; + 8'd49 : rd_data <= #1 -16'd20864; + 8'd50 : rd_data <= #1 16'd25925; + 8'd51 : rd_data <= #1 16'd27757; + 8'd52 : rd_data <= #1 -16'd30062; + 8'd53 : rd_data <= #1 -16'd28230; + 8'd54 : rd_data <= #1 16'd18560; + 8'd55 : rd_data <= #1 16'd20391; + 8'd56 : rd_data <= #1 -16'd19495; + 8'd57 : rd_data <= #1 -16'd17663; + 8'd58 : rd_data <= #1 16'd29126; + 8'd59 : rd_data <= #1 16'd30958; + 8'd60 : rd_data <= #1 -16'd26861; + 8'd61 : rd_data <= #1 -16'd25029; + 8'd62 : rd_data <= #1 16'd21761; + 8'd63 : rd_data <= #1 16'd23592; + 8'd64 : rd_data <= #1 -16'd25588; + 8'd65 : rd_data <= #1 16'd2293; + 8'd66 : rd_data <= #1 16'd2293; + 8'd67 : rd_data <= #1 16'd30174; + 8'd68 : rd_data <= #1 -16'd31788; + 8'd69 : rd_data <= #1 -16'd3907; + 8'd70 : rd_data <= #1 -16'd3907; + 8'd71 : rd_data <= #1 16'd23974; + 8'd72 : rd_data <= #1 -16'd24413; + 8'd73 : rd_data <= #1 16'd3468; + 8'd74 : rd_data <= #1 16'd3468; + 8'd75 : rd_data <= #1 16'd31349; + 8'd76 : rd_data <= #1 -16'd30613; + 8'd77 : rd_data <= #1 -16'd2732; + 8'd78 : rd_data <= #1 -16'd2732; + 8'd79 : rd_data <= #1 16'd25149; + 8'd80 : rd_data <= #1 -16'd25459; + 8'd81 : rd_data <= #1 16'd23162; + 8'd82 : rd_data <= #1 -16'd23628; + 8'd83 : rd_data <= #1 16'd24994; + 8'd84 : rd_data <= #1 -16'd24280; + 8'd85 : rd_data <= #1 16'd24341; + 8'd86 : rd_data <= #1 -16'd22449; + 8'd87 : rd_data <= #1 16'd26173; + 8'd88 : rd_data <= #1 -16'd26578; + 8'd89 : rd_data <= #1 16'd22044; + 8'd90 : rd_data <= #1 -16'd24746; + 8'd91 : rd_data <= #1 16'd23875; + 8'd92 : rd_data <= #1 -16'd25399; + 8'd93 : rd_data <= #1 16'd23222; + 8'd94 : rd_data <= #1 -16'd23567; + 8'd95 : rd_data <= #1 16'd25054; + 8'd96 : rd_data <= #1 -16'd23652; + 8'd97 : rd_data <= #1 -16'd14162; + 8'd98 : rd_data <= #1 16'd20256; + 8'd99 : rd_data <= #1 16'd29746; + 8'd100 : rd_data <= #1 -16'd32305; + 8'd101 : rd_data <= #1 -16'd22815; + 8'd102 : rd_data <= #1 16'd11602; + 8'd103 : rd_data <= #1 16'd21092; + 8'd104 : rd_data <= #1 -16'd20654; + 8'd105 : rd_data <= #1 -16'd11164; + 8'd106 : rd_data <= #1 16'd23253; + 8'd107 : rd_data <= #1 16'd32743; + 8'd108 : rd_data <= #1 -16'd29308; + 8'd109 : rd_data <= #1 -16'd19817; + 8'd110 : rd_data <= #1 16'd14600; + 8'd111 : rd_data <= #1 16'd24090; + 8'd112 : rd_data <= #1 -16'd26148; + 8'd113 : rd_data <= #1 16'd10555; + 8'd114 : rd_data <= #1 -16'd7681; + 8'd115 : rd_data <= #1 16'd29022; + 8'd116 : rd_data <= #1 -16'd29787; + 8'd117 : rd_data <= #1 16'd6917; + 8'd118 : rd_data <= #1 -16'd11319; + 8'd119 : rd_data <= #1 16'd25384; + 8'd120 : rd_data <= #1 -16'd26018; + 8'd121 : rd_data <= #1 16'd10685; + 8'd122 : rd_data <= #1 -16'd7550; + 8'd123 : rd_data <= #1 16'd29153; + 8'd124 : rd_data <= #1 -16'd29656; + 8'd125 : rd_data <= #1 16'd7047; + 8'd126 : rd_data <= #1 -16'd11189; + 8'd127 : rd_data <= #1 16'd25515; + 8'd128 : rd_data <= #1 -16'd23961; + 8'd129 : rd_data <= #1 16'd26300; + 8'd130 : rd_data <= #1 -16'd27846; + 8'd131 : rd_data <= #1 16'd22415; + 8'd132 : rd_data <= #1 -16'd21341; + 8'd133 : rd_data <= #1 16'd28920; + 8'd134 : rd_data <= #1 -16'd25226; + 8'd135 : rd_data <= #1 16'd25035; + 8'd136 : rd_data <= #1 -16'd25129; + 8'd137 : rd_data <= #1 16'd25132; + 8'd138 : rd_data <= #1 -16'd29014; + 8'd139 : rd_data <= #1 16'd21247; + 8'd140 : rd_data <= #1 -16'd22509; + 8'd141 : rd_data <= #1 16'd27753; + 8'd142 : rd_data <= #1 -16'd26394; + 8'd143 : rd_data <= #1 16'd23868; + 8'd144 : rd_data <= #1 -16'd24683; + 8'd145 : rd_data <= #1 -16'd6215; + 8'd146 : rd_data <= #1 16'd12020; + 8'd147 : rd_data <= #1 16'd30488; + 8'd148 : rd_data <= #1 -16'd32767; + 8'd149 : rd_data <= #1 -16'd14300; + 8'd150 : rd_data <= #1 16'd3936; + 8'd151 : rd_data <= #1 16'd22404; + 8'd152 : rd_data <= #1 -16'd22456; + 8'd153 : rd_data <= #1 -16'd3989; + 8'd154 : rd_data <= #1 16'd14247; + 8'd155 : rd_data <= #1 16'd32714; + 8'd156 : rd_data <= #1 -16'd30540; + 8'd157 : rd_data <= #1 -16'd12073; + 8'd158 : rd_data <= #1 16'd6163; + 8'd159 : rd_data <= #1 16'd24630; + 8'd160 : rd_data <= #1 -16'd26159; + 8'd161 : rd_data <= #1 16'd17748; + 8'd162 : rd_data <= #1 -16'd16669; + 8'd163 : rd_data <= #1 16'd27238; + 8'd164 : rd_data <= #1 -16'd27172; + 8'd165 : rd_data <= #1 16'd16736; + 8'd166 : rd_data <= #1 -16'd17682; + 8'd167 : rd_data <= #1 16'd26226; + 8'd168 : rd_data <= #1 -16'd26837; + 8'd169 : rd_data <= #1 16'd17070; + 8'd170 : rd_data <= #1 -16'd17347; + 8'd171 : rd_data <= #1 16'd26561; + 8'd172 : rd_data <= #1 -16'd27849; + 8'd173 : rd_data <= #1 16'd16058; + 8'd174 : rd_data <= #1 -16'd18359; + 8'd175 : rd_data <= #1 16'd25548; + 8'd176 : rd_data <= #1 -16'd22696; + 8'd177 : rd_data <= #1 -16'd20864; + 8'd178 : rd_data <= #1 16'd25925; + 8'd179 : rd_data <= #1 16'd27757; + 8'd180 : rd_data <= #1 -16'd30062; + 8'd181 : rd_data <= #1 -16'd28230; + 8'd182 : rd_data <= #1 16'd18560; + 8'd183 : rd_data <= #1 16'd20391; + 8'd184 : rd_data <= #1 -16'd19495; + 8'd185 : rd_data <= #1 -16'd17663; + 8'd186 : rd_data <= #1 16'd29126; + 8'd187 : rd_data <= #1 16'd30958; + 8'd188 : rd_data <= #1 -16'd26861; + 8'd189 : rd_data <= #1 -16'd25029; + 8'd190 : rd_data <= #1 16'd21761; + 8'd191 : rd_data <= #1 16'd23592; + 8'd192 : rd_data <= #1 -16'd25588; + 8'd193 : rd_data <= #1 16'd2293; + 8'd194 : rd_data <= #1 16'd2293; + 8'd195 : rd_data <= #1 16'd30174; + 8'd196 : rd_data <= #1 -16'd31788; + 8'd197 : rd_data <= #1 -16'd3907; + 8'd198 : rd_data <= #1 -16'd3907; + 8'd199 : rd_data <= #1 16'd23974; + 8'd200 : rd_data <= #1 -16'd24413; + 8'd201 : rd_data <= #1 16'd3468; + 8'd202 : rd_data <= #1 16'd3468; + 8'd203 : rd_data <= #1 16'd31349; + 8'd204 : rd_data <= #1 -16'd30613; + 8'd205 : rd_data <= #1 -16'd2732; + 8'd206 : rd_data <= #1 -16'd2732; + 8'd207 : rd_data <= #1 16'd25149; + 8'd208 : rd_data <= #1 -16'd25459; + 8'd209 : rd_data <= #1 16'd23162; + 8'd210 : rd_data <= #1 -16'd23628; + 8'd211 : rd_data <= #1 16'd24994; + 8'd212 : rd_data <= #1 -16'd24280; + 8'd213 : rd_data <= #1 16'd24341; + 8'd214 : rd_data <= #1 -16'd22449; + 8'd215 : rd_data <= #1 16'd26173; + 8'd216 : rd_data <= #1 -16'd26578; + 8'd217 : rd_data <= #1 16'd22044; + 8'd218 : rd_data <= #1 -16'd24746; + 8'd219 : rd_data <= #1 16'd23875; + 8'd220 : rd_data <= #1 -16'd25399; + 8'd221 : rd_data <= #1 16'd23222; + 8'd222 : rd_data <= #1 -16'd23567; + 8'd223 : rd_data <= #1 16'd25054; + 8'd224 : rd_data <= #1 -16'd23652; + 8'd225 : rd_data <= #1 -16'd14162; + 8'd226 : rd_data <= #1 16'd20256; + 8'd227 : rd_data <= #1 16'd29746; + 8'd228 : rd_data <= #1 -16'd32305; + 8'd229 : rd_data <= #1 -16'd22815; + 8'd230 : rd_data <= #1 16'd11602; + 8'd231 : rd_data <= #1 16'd21092; + 8'd232 : rd_data <= #1 -16'd20654; + 8'd233 : rd_data <= #1 -16'd11164; + 8'd234 : rd_data <= #1 16'd23253; + 8'd235 : rd_data <= #1 16'd32743; + 8'd236 : rd_data <= #1 -16'd29308; + 8'd237 : rd_data <= #1 -16'd19817; + 8'd238 : rd_data <= #1 16'd14600; + 8'd239 : rd_data <= #1 16'd24090; + 8'd240 : rd_data <= #1 -16'd26148; + 8'd241 : rd_data <= #1 16'd10555; + 8'd242 : rd_data <= #1 -16'd7681; + 8'd243 : rd_data <= #1 16'd29022; + 8'd244 : rd_data <= #1 -16'd29787; + 8'd245 : rd_data <= #1 16'd6917; + 8'd246 : rd_data <= #1 -16'd11319; + 8'd247 : rd_data <= #1 16'd25384; + 8'd248 : rd_data <= #1 -16'd26018; + 8'd249 : rd_data <= #1 16'd10685; + 8'd250 : rd_data <= #1 -16'd7550; + 8'd251 : rd_data <= #1 16'd29153; + 8'd252 : rd_data <= #1 -16'd29656; + 8'd253 : rd_data <= #1 16'd7047; + 8'd254 : rd_data <= #1 -16'd11189; + 8'd255 : rd_data <= #1 16'd25515; + endcase // case(rd_addr) + end //if (strobe) + assign out_data[15:0]=reg_quadrant?-rd_data:rd_data; + sign_extend #(16,18) + ext_output (.in(out_data),.out(ext_out_data)); + +endmodule // rrc_coeff_ram_generated_1 + +//bw= 10 data_size= 1 abs_max= 289 len= 1 +module rrc_coeff_ram_generated0_2 (input clock, input strobe, input [3:0] phase, input [0:0] in_data, output [9:0] out_data,output [17:0] ext_out_data); + +reg reg_quadrant; +wire quadrant=in_data[0]; +wire [3:0] rd_addr=phase; +reg [9:0] rd_data; + + always @(posedge clock) + if (strobe) + begin + reg_quadrant <= #1 quadrant; + case (rd_addr) + 4'd0 : rd_data <= #1 -10'd172; + 4'd1 : rd_data <= #1 10'd289; + 4'd2 : rd_data <= #1 10'd55; + 4'd3 : rd_data <= #1 10'd114; + 4'd4 : rd_data <= #1 10'd267; + 4'd5 : rd_data <= #1 -10'd73; + 4'd6 : rd_data <= #1 10'd236; + 4'd7 : rd_data <= #1 10'd179; + 4'd8 : rd_data <= #1 -10'd172; + 4'd9 : rd_data <= #1 10'd289; + 4'd10 : rd_data <= #1 10'd55; + 4'd11 : rd_data <= #1 10'd114; + 4'd12 : rd_data <= #1 10'd267; + 4'd13 : rd_data <= #1 -10'd73; + 4'd14 : rd_data <= #1 10'd236; + 4'd15 : rd_data <= #1 10'd179; + endcase // case(rd_addr) + end //if (strobe) + assign out_data[9:0]=reg_quadrant?-rd_data:rd_data; + sign_extend #(10,18) + ext_output (.in(out_data),.out(ext_out_data)); + +endmodule // rrc_coeff_ram_generated_2 + +//bw_memory [4, 4, 0] data_size 5 +module frac_interp_0 + + (input clock, input reset, input enable, + output reg strobe_in, input strobe_out, + input wire [4:0] tx_shift, + input wire [15:0] signal_in, + output reg [15:0] signal_out); + +reg [3:0] phase;//max 16 phases + +reg [3:0] in_count;//16 bits in every register + +reg [15:0] input_16; + +reg [15:0] shift_16_0; +wire get_bit= (phase==4'd1) || (phase==4'd3) || (phase==4'd4) || (phase==4'd6) || (phase==4'd7) || (phase==4'd9) || (phase==4'd11) || (phase==4'd12) || (phase==4'd14) || (phase==4'd15); + + always @(posedge clock) + if (reset) + begin + strobe_in <= #1 0;// Reset + in_count <=#1 0; + input_16 <= #1 0; + + shift_16_0 <= #1 0; + + end //if (reset) + else //if (reset) + begin + if(enable & strobe_out & get_bit & (in_count == 4'd15)) + strobe_in <=#1 1'd1;//Only works if output of previous stage is registered and only updates on this strobe_in + else // if(strobe_in) //input a new 16 bit word and shift all regs 16 bit to the right= to next register) + strobe_in <= #1 0;//notice the else is always executed, even if there is no strobe_out so strobe_in will only be high for 1 clock + + if (enable & strobe_out) + begin + if ( get_bit) + + begin //shift input 1 bit to the left + if(in_count == 4'd15) //(strobe_in) //if(in_count == 4'd0) + begin + //strobe_in <=#1 1'd1;//Only works if output of previous stage is registered and only updates on this strobe_in + input_16 <= #1 signal_in; + end //if(in_count == 4'd0) + else //if(in_count == 4'd0) + begin + input_16 <= #1 {1'd0,input_16[15:1]};//just shift right //MDVH 14feb2007 + //input_16 <= #1 {input_16[14:0],1'd0};//just shift left //MDVH 14feb2007 + end // if(in_count == 4'd0) else + //shift_16_0 <= #1 {shift_16_0[14:0],input_16[15]};//MDVH 14feb2007 + shift_16_0 <= #1 {input_16[0],shift_16_0[15:1]};//MDVH 14feb2007 + + + in_count <= #1 in_count+4'd1; + end //if ((phase==.... + end //if (enable & strobe_out) + end // if (reset) else + + always @(posedge clock) + if (reset) + phase <=#1 0; + else if (enable & strobe_out) + phase <=#1 phase + 4'd1;//phase will roll-over to zero and start again + + +wire [4:0] data_0; +wire [4:0] data_1; +wire [0:0] data_2; +assign data_2=shift_16_0[10:10]; +assign data_1=shift_16_0[9:5]; +assign data_0=shift_16_0[4:0]; +wire [17:0] sum_0; +wire [17:0] sum_1; +wire [17:0] sum_2; +wire [17:0] sum_3; +assign sum_3=0; +reg [17:0] sum_all; + +//wire [15:0] sum_all_16bit; + + rrc_coeff_ram_generated0_0 rrc_coeff_ram_0 ( .clock(clock),.strobe(strobe_out),.phase(phase),.in_data(data_0),.out_data(),.ext_out_data(sum_0) ); + rrc_coeff_ram_generated0_1 rrc_coeff_ram_1 ( .clock(clock),.strobe(strobe_out),.phase(phase),.in_data(data_1),.out_data(),.ext_out_data(sum_1) ); + rrc_coeff_ram_generated0_2 rrc_coeff_ram_2 ( .clock(clock),.strobe(strobe_out),.phase(phase),.in_data(data_2),.out_data(),.ext_out_data(sum_2) ); +//assign sum_all= sum_0 + sum_1 + sum_2; +reg [17:0] sum_01; +reg [17:0] sum_23; +reg [17:0] sum_0123; + + always @(posedge clock) + if (reset) + begin + + sum_01 <= #1 0; + sum_23 <= #1 0; + sum_0123 <= #1 0; + + sum_all <=#1 0; + signal_out <= #1 0; + end + else if (enable & strobe_out) + begin + + sum_01 <= #1 sum_0+sum_1; + sum_23 <= #1 sum_2+sum_3; + sum_0123 <= #1 sum_01+sum_23; + sum_all <= #1 sum_0123; + + case(tx_shift) + //5'd0 : signal_out <= #1 round_16(sum_all);//no gain reduce + 5'd0 : signal_out <= #1 { sum_all[16:1] + (sum_all[17] & ( sum_all[0] )) }; + 5'd1 : signal_out <= #1 { sum_all[17:2] + (sum_all[17] & (|sum_all[1:0])) }; + 5'd2 : signal_out <= #1 { {{(1){sum_all[17]}}, sum_all[17:3]} + (sum_all[17] & (|sum_all[2:0])) }; + 5'd3 : signal_out <= #1 { {{(2){sum_all[17]}}, sum_all[17:4]} + (sum_all[17] & (|sum_all[3:0])) }; + 5'd4 : signal_out <= #1 { {{(3){sum_all[17]}}, sum_all[17:5]} + (sum_all[17] & (|sum_all[4:0])) }; + 5'd5 : signal_out <= #1 { {{(4){sum_all[17]}}, sum_all[17:6]} + (sum_all[17] & (|sum_all[5:0])) }; + 5'd6 : signal_out <= #1 { {{(5){sum_all[17]}}, sum_all[17:7]} + (sum_all[17] & (|sum_all[6:0])) }; + 5'd7 : signal_out <= #1 { {{(6){sum_all[17]}}, sum_all[17:8]} + (sum_all[17] & (|sum_all[7:0])) }; + 5'd8 : signal_out <= #1 { {{(7){sum_all[17]}}, sum_all[17:9]} + (sum_all[17] & (|sum_all[8:0])) }; + 5'd9 : signal_out <= #1 { {{(8){sum_all[17]}}, sum_all[17:10]} + (sum_all[17] & (|sum_all[9:0])) }; + 5'd10 : signal_out <= #1 { {{(9){sum_all[17]}},sum_all[17:11]} + (sum_all[17] & (|sum_all[10:0]))}; + 5'd11 : signal_out <= #1 { {{(10){sum_all[17]}},sum_all[17:12]} + (sum_all[17] & (|sum_all[11:0]))}; + 5'd12 : signal_out <= #1 { {{(11){sum_all[17]}},sum_all[17:13]} + (sum_all[17] & (|sum_all[12:0]))}; + 5'd13 : signal_out <= #1 { {{(12){sum_all[17]}},sum_all[17:14]} + (sum_all[17] & (|sum_all[13:0]))}; + 5'd14 : signal_out <= #1 { {{(13){sum_all[17]}},sum_all[17:15]} + (sum_all[17] & (|sum_all[14:0]))}; + 5'd15 : signal_out <= #1 { {{(14){sum_all[17]}},sum_all[17:16]} + (sum_all[17] & (|sum_all[15:0]))}; + + -5'd1 : signal_out <= #1 {sum_all[15:0] }; + -5'd2 : signal_out <= #1 {sum_all[14:0] ,{(1){1'b0}}}; + -5'd3 : signal_out <= #1 {sum_all[13:0] ,{(2){1'b0}}}; + -5'd4 : signal_out <= #1 {sum_all[12:0] ,{(3){1'b0}}}; + -5'd5 : signal_out <= #1 {sum_all[11:0] ,{(4){1'b0}}}; + -5'd6 : signal_out <= #1 {sum_all[10:0] ,{(5){1'b0}}}; + -5'd7 : signal_out <= #1 {sum_all[9:0] ,{(6){1'b0}}}; + -5'd8 : signal_out <= #1 {sum_all[8:0] ,{(7){1'b0}}}; + -5'd9 : signal_out <= #1 {sum_all[7:0] ,{(8){1'b0}}}; + -5'd10 : signal_out <= #1 {sum_all[6:0] ,{(9){1'b0}}}; + -5'd11 : signal_out <= #1 {sum_all[5:0] ,{(10){1'b0}}}; + -5'd12 : signal_out <= #1 {sum_all[4:0] ,{(11){1'b0}}}; + -5'd13 : signal_out <= #1 {sum_all[3:0] ,{(12){1'b0}}}; + -5'd14 : signal_out <= #1 {sum_all[2:0] ,{(13){1'b0}}}; + -5'd15 : signal_out <= #1 {sum_all[1:0] ,{(14){1'b0}}}; + + default : signal_out <= #1 { sum_all[16:1] + (sum_all[17] & ( sum_all[0] )) }; + //signal_out <= #1 { sum_all[17:2] + (sum_all[17] & (|sum_all[1:0])) }; + endcase // case(shift) + + //sum_all_14bit <= #1 sum_0123[16:3] + (sum_0123[16] & |sum_0123[2:0]);//round to 14 bit (reduce gain by 2 bit = 12 dB) + + //signal_out <= #1 round_16(sum_all);//no gain reduce + //signal_out <= #1 {{(2){sum_all_14bit[13]}},sum_all_14bit};//sign_extend to 16 bit (gain reduced by 2 bit = 12 dB) + + end //else if (enable & strobe_out) + + +/*assign sum_all_16bit=round_16(sum_all); +//register the output to ease timing of the DDR DAC output + always @(posedge clock or posedge reset) + if (reset) + signal_out <= #1 0; // Reset + else + signal_out <= #1 sum_all_16bit; +*/ +//round to 16 bit +// function [15:0] round_16; +// input [16:0] in_val; +// round_16 = in_val[16:1] + (in_val[16] & |in_val[0]);//round_16 = in_val[16:1] + (in_val[16] & in_val[0]) +// endfunction // round_16 + + +endmodule //module frac_interp_0 Index: usrp/fpga/sdr_lib/frac_interp_alpha0.35_int16_dec10_DACint4X_chan1.v =================================================================== --- usrp/fpga/sdr_lib/frac_interp_alpha0.35_int16_dec10_DACint4X_chan1.v (revision 0) +++ usrp/fpga/sdr_lib/frac_interp_alpha0.35_int16_dec10_DACint4X_chan1.v (revision 0) @@ -0,0 +1,879 @@ +// -*- verilog -*- +// +// Polyphase interpolating Root-Raised-Cosine filter +// +// Copyright (C) 2007 Martin Dudok van Heel +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// +// Polyphase interpolating Root-Raised-Cosine filter +// Interpolation ratio can be fractional (float) +// +// This file was generated by ./generate_frac_interp_05nov2007.py at 2007-11-08 00:15:22.495115 +// Written by Martin Dudok van Heel, 2007 +// Olifantasia +// +// Contact: http://www.olifantasia.com/gnuradio/contact.gif or nldudok1_olifantasia_com +// http://www.olifantasia.com +// +// This file can be used to build a special purpose firmware for the USRP +// USRP = Universal Software Radio Peripheral +// This special purpose firmware in combination with the GnuRadio framework can be used to create a high speed QPSK transmitter +// Depending on the decimation and interpolation factors used, the symbolrate can be from 2 to 20 Msymbols/sec +// The corresponding QPSK bitrate is 4 to 40 Mbit/sec +// alpha= 0.35 +// interpolation = 16.0 decimation= 10.0 interp_ratio= 1.6 decim_ratio= 0.625 +// symbol rate = 20.0 Msymbol/sec +// QPSK bitrate = 40.0 Mbit/sec +// +//fractional ntaps 17.6 +//ntaps_per_filter= 11 +//nfilters= 16 +// s f incr d_mu ii oo step +// 0.0 0.0 0 0.0 0 0 0 +// 0.625 0.0 0 0.625 0 1 1 +// 1.25 1.0 1 0.25 1 2 2 +// 0.875 0.0 0 0.875 1 3 3 +// 1.5 1.0 1 0.5 2 4 4 +// 1.125 1.0 1 0.125 3 5 5 +// 0.75 0.0 0 0.75 3 6 6 +// 1.375 1.0 1 0.375 4 7 7 +// 1.0 1.0 1 0.0 5 8 8 +// 0.625 0.0 0 0.625 5 9 9 +// 1.25 1.0 1 0.25 6 10 10 +// 0.875 0.0 0 0.875 6 11 11 +// 1.5 1.0 1 0.5 7 12 12 +// 1.125 1.0 1 0.125 8 13 13 +// 0.75 0.0 0 0.75 8 14 14 +// 1.375 1.0 1 0.375 9 15 15 +//poly_filter[ 0 ] = +// [0.0075129163196754143, 0.0020458085258023588, -0.025488551496836223, 0.057197572717172032, -0.084806311229650128, 1.0971351131785818, -0.084806311229650128, 0.057197572717172032, -0.025488551496836223, 0.0020458085258023588, 0.0075129163196754143] + +//poly_filter[ 1 ] = +// [-0.0013039776546781791, -0.0078269741673739467, 0.013835225353669441, 0.002852740888603599, -0.079417311797210149, 0.40311908078699055, 0.80118104720156236, -0.17646842387834014, 0.048603951449408038, 0.0011463481286299721, -0.01263496157797927] + +//poly_filter[ 2 ] = +// [0.0092022137140799678, -0.010284732153928977, -0.0095621618982352288, 0.065433931294967412, -0.18889153520490076, 0.95843746473199454, 0.20715466856520273, -0.022102879562705985, -0.014795407502031947, 0.013338514291149838, -0.0023810270307585914] + +//poly_filter[ 3 ] = +// [-0.0061008521195972838, 0.0031972964531200854, 0.0088445847910837132, -0.024414733630969649, 0.025733284007473971, 0.03998468989127623, 1.0613394960075577, -0.16078491709665643, 0.069870145274482917, -0.019566539655389181, -0.0049678758232720738] + +//poly_filter[ 4 ] = +// [0.0027539244869444345, -0.011642548473894643, 0.009585493131322181, 0.025650092551220097, -0.13534932275453265, 0.60860640890431328, 0.60860640890431328, -0.13534932275453265, 0.025650092551220097, 0.009585493131322181, -0.011642548473894643] + +//poly_filter[ 5 ] = +// [0.0096164209789455068, -0.0049678758232720738, -0.019566539655389181, 0.069870145274482917, -0.16078491709665643, 1.0613394960075577, 0.03998468989127623, 0.025733284007473971, -0.024414733630969649, 0.0088445847910837132, 0.0031972964531200854] + +//poly_filter[ 6 ] = +// [-0.0044979561915869572, -0.0023810270307585914, 0.013338514291149838, -0.014795407502031947, -0.022102879562705985, 0.20715466856520273, 0.95843746473199454, -0.18889153520490076, 0.065433931294967412, -0.0095621618982352288, -0.010284732153928977] + +//poly_filter[ 7 ] = +// [0.0066260209432802133, -0.01263496157797927, 0.0011463481286299721, 0.048603951449408038, -0.17646842387834014, 0.80118104720156236, 0.40311908078699055, -0.079417311797210149, 0.002852740888603599, 0.013835225353669441, -0.0078269741673739467] + +//poly_filter[ 8 ] = +// [0.0075129163196754143, 0.0020458085258023588, -0.025488551496836223, 0.057197572717172032, -0.084806311229650128, 1.0971351131785818, -0.084806311229650128, 0.057197572717172032, -0.025488551496836223, 0.0020458085258023588, 0.0075129163196754143] + +//poly_filter[ 9 ] = +// [-0.0013039776546781791, -0.0078269741673739467, 0.013835225353669441, 0.002852740888603599, -0.079417311797210149, 0.40311908078699055, 0.80118104720156236, -0.17646842387834014, 0.048603951449408038, 0.0011463481286299721, -0.01263496157797927] + +//poly_filter[ 10 ] = +// [0.0092022137140799678, -0.010284732153928977, -0.0095621618982352288, 0.065433931294967412, -0.18889153520490076, 0.95843746473199454, 0.20715466856520273, -0.022102879562705985, -0.014795407502031947, 0.013338514291149838, -0.0023810270307585914] + +//poly_filter[ 11 ] = +// [-0.0061008521195972838, 0.0031972964531200854, 0.0088445847910837132, -0.024414733630969649, 0.025733284007473971, 0.03998468989127623, 1.0613394960075577, -0.16078491709665643, 0.069870145274482917, -0.019566539655389181, -0.0049678758232720738] + +//poly_filter[ 12 ] = +// [0.0027539244869444345, -0.011642548473894643, 0.009585493131322181, 0.025650092551220097, -0.13534932275453265, 0.60860640890431328, 0.60860640890431328, -0.13534932275453265, 0.025650092551220097, 0.009585493131322181, -0.011642548473894643] + +//poly_filter[ 13 ] = +// [0.0096164209789455068, -0.0049678758232720738, -0.019566539655389181, 0.069870145274482917, -0.16078491709665643, 1.0613394960075577, 0.03998468989127623, 0.025733284007473971, -0.024414733630969649, 0.0088445847910837132, 0.0031972964531200854] + +//poly_filter[ 14 ] = +// [-0.0044979561915869572, -0.0023810270307585914, 0.013338514291149838, -0.014795407502031947, -0.022102879562705985, 0.20715466856520273, 0.95843746473199454, -0.18889153520490076, 0.065433931294967412, -0.0095621618982352288, -0.010284732153928977] + +//poly_filter[ 15 ] = +// [0.0066260209432802133, -0.01263496157797927, 0.0011463481286299721, 0.048603951449408038, -0.17646842387834014, 0.80118104720156236, 0.40311908078699055, -0.079417311797210149, 0.002852740888603599, 0.013835225353669441, -0.0078269741673739467] + +// total_ntaps= 176 +// ntaps_per_filter= 11 +// nfilters= 16 +// filter resolution= 16 bits +// +//data_size= 5 phase_size= 4 +//abs_max= 1.43051885144 abs_max_16bit= 32767 signed_max_16bit= 32743 signed_min_16bit= -32767 +//nmemories= 3 +//incr_list = [1, 3, 4, 6, 7, 9, 11, 12, 14, 15] +//bw= 14 data_size= 5 abs_max= 6491 len= 16 +module rrc_coeff_ram_generated1_0 (input clock, input strobe, input [3:0] phase, input [4:0] in_data, output [13:0] out_data,output [17:0] ext_out_data); + +reg reg_quadrant; +wire quadrant=in_data[4]; +wire [7:0] rd_addr={phase,quadrant?~in_data[3:0]:in_data[3:0]}; +reg [13:0] rd_data; + + always @(posedge clock) + if (strobe) + begin + reg_quadrant <= #1 quadrant; + case (rd_addr) + 8'd0 : rd_data <= #1 14'd997; + 8'd1 : rd_data <= #1 14'd1341; + 8'd2 : rd_data <= #1 14'd1091; + 8'd3 : rd_data <= #1 14'd1435; + 8'd4 : rd_data <= #1 -14'd170; + 8'd5 : rd_data <= #1 14'd174; + 8'd6 : rd_data <= #1 -14'd77; + 8'd7 : rd_data <= #1 14'd268; + 8'd8 : rd_data <= #1 14'd3618; + 8'd9 : rd_data <= #1 14'd3962; + 8'd10 : rd_data <= #1 14'd3711; + 8'd11 : rd_data <= #1 14'd4055; + 8'd12 : rd_data <= #1 14'd2450; + 8'd13 : rd_data <= #1 14'd2794; + 8'd14 : rd_data <= #1 14'd2544; + 8'd15 : rd_data <= #1 14'd2888; + 8'd16 : rd_data <= #1 14'd1646; + 8'd17 : rd_data <= #1 14'd1586; + 8'd18 : rd_data <= #1 14'd1287; + 8'd19 : rd_data <= #1 14'd1228; + 8'd20 : rd_data <= #1 14'd2280; + 8'd21 : rd_data <= #1 14'd2220; + 8'd22 : rd_data <= #1 14'd1921; + 8'd23 : rd_data <= #1 14'd1862; + 8'd24 : rd_data <= #1 14'd1777; + 8'd25 : rd_data <= #1 14'd1717; + 8'd26 : rd_data <= #1 14'd1418; + 8'd27 : rd_data <= #1 14'd1358; + 8'd28 : rd_data <= #1 14'd2411; + 8'd29 : rd_data <= #1 14'd2351; + 8'd30 : rd_data <= #1 14'd2052; + 8'd31 : rd_data <= #1 14'd1992; + 8'd32 : rd_data <= #1 14'd3072; + 8'd33 : rd_data <= #1 14'd3493; + 8'd34 : rd_data <= #1 14'd2601; + 8'd35 : rd_data <= #1 14'd3022; + 8'd36 : rd_data <= #1 14'd2634; + 8'd37 : rd_data <= #1 14'd3055; + 8'd38 : rd_data <= #1 14'd2162; + 8'd39 : rd_data <= #1 14'd2584; + 8'd40 : rd_data <= #1 14'd6069; + 8'd41 : rd_data <= #1 14'd6491; + 8'd42 : rd_data <= #1 14'd5598; + 8'd43 : rd_data <= #1 14'd6020; + 8'd44 : rd_data <= #1 14'd5631; + 8'd45 : rd_data <= #1 14'd6053; + 8'd46 : rd_data <= #1 14'd5160; + 8'd47 : rd_data <= #1 14'd5582; + 8'd48 : rd_data <= #1 -14'd166; + 8'd49 : rd_data <= #1 -14'd446; + 8'd50 : rd_data <= #1 -14'd20; + 8'd51 : rd_data <= #1 -14'd299; + 8'd52 : rd_data <= #1 14'd239; + 8'd53 : rd_data <= #1 -14'd41; + 8'd54 : rd_data <= #1 14'd385; + 8'd55 : rd_data <= #1 14'd106; + 8'd56 : rd_data <= #1 -14'd1285; + 8'd57 : rd_data <= #1 -14'd1564; + 8'd58 : rd_data <= #1 -14'd1138; + 8'd59 : rd_data <= #1 -14'd1418; + 8'd60 : rd_data <= #1 -14'd880; + 8'd61 : rd_data <= #1 -14'd1159; + 8'd62 : rd_data <= #1 -14'd733; + 8'd63 : rd_data <= #1 -14'd1013; + 8'd64 : rd_data <= #1 14'd2497; + 8'd65 : rd_data <= #1 14'd2623; + 8'd66 : rd_data <= #1 14'd1963; + 8'd67 : rd_data <= #1 14'd2090; + 8'd68 : rd_data <= #1 14'd2936; + 8'd69 : rd_data <= #1 14'd3062; + 8'd70 : rd_data <= #1 14'd2403; + 8'd71 : rd_data <= #1 14'd2529; + 8'd72 : rd_data <= #1 14'd3672; + 8'd73 : rd_data <= #1 14'd3798; + 8'd74 : rd_data <= #1 14'd3138; + 8'd75 : rd_data <= #1 14'd3265; + 8'd76 : rd_data <= #1 14'd4111; + 8'd77 : rd_data <= #1 14'd4237; + 8'd78 : rd_data <= #1 14'd3578; + 8'd79 : rd_data <= #1 14'd3704; + 8'd80 : rd_data <= #1 14'd2424; + 8'd81 : rd_data <= #1 14'd2865; + 8'd82 : rd_data <= #1 14'd2197; + 8'd83 : rd_data <= #1 14'd2637; + 8'd84 : rd_data <= #1 14'd1528; + 8'd85 : rd_data <= #1 14'd1968; + 8'd86 : rd_data <= #1 14'd1300; + 8'd87 : rd_data <= #1 14'd1741; + 8'd88 : rd_data <= #1 14'd5625; + 8'd89 : rd_data <= #1 14'd6066; + 8'd90 : rd_data <= #1 14'd5397; + 8'd91 : rd_data <= #1 14'd5838; + 8'd92 : rd_data <= #1 14'd4729; + 8'd93 : rd_data <= #1 14'd5169; + 8'd94 : rd_data <= #1 14'd4501; + 8'd95 : rd_data <= #1 14'd4942; + 8'd96 : rd_data <= #1 14'd697; + 8'd97 : rd_data <= #1 14'd491; + 8'd98 : rd_data <= #1 14'd588; + 8'd99 : rd_data <= #1 14'd382; + 8'd100 : rd_data <= #1 14'd1308; + 8'd101 : rd_data <= #1 14'd1102; + 8'd102 : rd_data <= #1 14'd1199; + 8'd103 : rd_data <= #1 14'd993; + 8'd104 : rd_data <= #1 14'd19; + 8'd105 : rd_data <= #1 -14'd187; + 8'd106 : rd_data <= #1 -14'd90; + 8'd107 : rd_data <= #1 -14'd296; + 8'd108 : rd_data <= #1 14'd630; + 8'd109 : rd_data <= #1 14'd424; + 8'd110 : rd_data <= #1 14'd521; + 8'd111 : rd_data <= #1 14'd315; + 8'd112 : rd_data <= #1 14'd3040; + 8'd113 : rd_data <= #1 14'd3344; + 8'd114 : rd_data <= #1 14'd2461; + 8'd115 : rd_data <= #1 14'd2765; + 8'd116 : rd_data <= #1 14'd3093; + 8'd117 : rd_data <= #1 14'd3396; + 8'd118 : rd_data <= #1 14'd2514; + 8'd119 : rd_data <= #1 14'd2817; + 8'd120 : rd_data <= #1 14'd5267; + 8'd121 : rd_data <= #1 14'd5570; + 8'd122 : rd_data <= #1 14'd4688; + 8'd123 : rd_data <= #1 14'd4992; + 8'd124 : rd_data <= #1 14'd5319; + 8'd125 : rd_data <= #1 14'd5623; + 8'd126 : rd_data <= #1 14'd4741; + 8'd127 : rd_data <= #1 14'd5044; + 8'd128 : rd_data <= #1 14'd997; + 8'd129 : rd_data <= #1 14'd1341; + 8'd130 : rd_data <= #1 14'd1091; + 8'd131 : rd_data <= #1 14'd1435; + 8'd132 : rd_data <= #1 -14'd170; + 8'd133 : rd_data <= #1 14'd174; + 8'd134 : rd_data <= #1 -14'd77; + 8'd135 : rd_data <= #1 14'd268; + 8'd136 : rd_data <= #1 14'd3618; + 8'd137 : rd_data <= #1 14'd3962; + 8'd138 : rd_data <= #1 14'd3711; + 8'd139 : rd_data <= #1 14'd4055; + 8'd140 : rd_data <= #1 14'd2450; + 8'd141 : rd_data <= #1 14'd2794; + 8'd142 : rd_data <= #1 14'd2544; + 8'd143 : rd_data <= #1 14'd2888; + 8'd144 : rd_data <= #1 14'd1646; + 8'd145 : rd_data <= #1 14'd1586; + 8'd146 : rd_data <= #1 14'd1287; + 8'd147 : rd_data <= #1 14'd1228; + 8'd148 : rd_data <= #1 14'd2280; + 8'd149 : rd_data <= #1 14'd2220; + 8'd150 : rd_data <= #1 14'd1921; + 8'd151 : rd_data <= #1 14'd1862; + 8'd152 : rd_data <= #1 14'd1777; + 8'd153 : rd_data <= #1 14'd1717; + 8'd154 : rd_data <= #1 14'd1418; + 8'd155 : rd_data <= #1 14'd1358; + 8'd156 : rd_data <= #1 14'd2411; + 8'd157 : rd_data <= #1 14'd2351; + 8'd158 : rd_data <= #1 14'd2052; + 8'd159 : rd_data <= #1 14'd1992; + 8'd160 : rd_data <= #1 14'd3072; + 8'd161 : rd_data <= #1 14'd3493; + 8'd162 : rd_data <= #1 14'd2601; + 8'd163 : rd_data <= #1 14'd3022; + 8'd164 : rd_data <= #1 14'd2634; + 8'd165 : rd_data <= #1 14'd3055; + 8'd166 : rd_data <= #1 14'd2162; + 8'd167 : rd_data <= #1 14'd2584; + 8'd168 : rd_data <= #1 14'd6069; + 8'd169 : rd_data <= #1 14'd6491; + 8'd170 : rd_data <= #1 14'd5598; + 8'd171 : rd_data <= #1 14'd6020; + 8'd172 : rd_data <= #1 14'd5631; + 8'd173 : rd_data <= #1 14'd6053; + 8'd174 : rd_data <= #1 14'd5160; + 8'd175 : rd_data <= #1 14'd5582; + 8'd176 : rd_data <= #1 -14'd166; + 8'd177 : rd_data <= #1 -14'd446; + 8'd178 : rd_data <= #1 -14'd20; + 8'd179 : rd_data <= #1 -14'd299; + 8'd180 : rd_data <= #1 14'd239; + 8'd181 : rd_data <= #1 -14'd41; + 8'd182 : rd_data <= #1 14'd385; + 8'd183 : rd_data <= #1 14'd106; + 8'd184 : rd_data <= #1 -14'd1285; + 8'd185 : rd_data <= #1 -14'd1564; + 8'd186 : rd_data <= #1 -14'd1138; + 8'd187 : rd_data <= #1 -14'd1418; + 8'd188 : rd_data <= #1 -14'd880; + 8'd189 : rd_data <= #1 -14'd1159; + 8'd190 : rd_data <= #1 -14'd733; + 8'd191 : rd_data <= #1 -14'd1013; + 8'd192 : rd_data <= #1 14'd2497; + 8'd193 : rd_data <= #1 14'd2623; + 8'd194 : rd_data <= #1 14'd1963; + 8'd195 : rd_data <= #1 14'd2090; + 8'd196 : rd_data <= #1 14'd2936; + 8'd197 : rd_data <= #1 14'd3062; + 8'd198 : rd_data <= #1 14'd2403; + 8'd199 : rd_data <= #1 14'd2529; + 8'd200 : rd_data <= #1 14'd3672; + 8'd201 : rd_data <= #1 14'd3798; + 8'd202 : rd_data <= #1 14'd3138; + 8'd203 : rd_data <= #1 14'd3265; + 8'd204 : rd_data <= #1 14'd4111; + 8'd205 : rd_data <= #1 14'd4237; + 8'd206 : rd_data <= #1 14'd3578; + 8'd207 : rd_data <= #1 14'd3704; + 8'd208 : rd_data <= #1 14'd2424; + 8'd209 : rd_data <= #1 14'd2865; + 8'd210 : rd_data <= #1 14'd2197; + 8'd211 : rd_data <= #1 14'd2637; + 8'd212 : rd_data <= #1 14'd1528; + 8'd213 : rd_data <= #1 14'd1968; + 8'd214 : rd_data <= #1 14'd1300; + 8'd215 : rd_data <= #1 14'd1741; + 8'd216 : rd_data <= #1 14'd5625; + 8'd217 : rd_data <= #1 14'd6066; + 8'd218 : rd_data <= #1 14'd5397; + 8'd219 : rd_data <= #1 14'd5838; + 8'd220 : rd_data <= #1 14'd4729; + 8'd221 : rd_data <= #1 14'd5169; + 8'd222 : rd_data <= #1 14'd4501; + 8'd223 : rd_data <= #1 14'd4942; + 8'd224 : rd_data <= #1 14'd697; + 8'd225 : rd_data <= #1 14'd491; + 8'd226 : rd_data <= #1 14'd588; + 8'd227 : rd_data <= #1 14'd382; + 8'd228 : rd_data <= #1 14'd1308; + 8'd229 : rd_data <= #1 14'd1102; + 8'd230 : rd_data <= #1 14'd1199; + 8'd231 : rd_data <= #1 14'd993; + 8'd232 : rd_data <= #1 14'd19; + 8'd233 : rd_data <= #1 -14'd187; + 8'd234 : rd_data <= #1 -14'd90; + 8'd235 : rd_data <= #1 -14'd296; + 8'd236 : rd_data <= #1 14'd630; + 8'd237 : rd_data <= #1 14'd424; + 8'd238 : rd_data <= #1 14'd521; + 8'd239 : rd_data <= #1 14'd315; + 8'd240 : rd_data <= #1 14'd3040; + 8'd241 : rd_data <= #1 14'd3344; + 8'd242 : rd_data <= #1 14'd2461; + 8'd243 : rd_data <= #1 14'd2765; + 8'd244 : rd_data <= #1 14'd3093; + 8'd245 : rd_data <= #1 14'd3396; + 8'd246 : rd_data <= #1 14'd2514; + 8'd247 : rd_data <= #1 14'd2817; + 8'd248 : rd_data <= #1 14'd5267; + 8'd249 : rd_data <= #1 14'd5570; + 8'd250 : rd_data <= #1 14'd4688; + 8'd251 : rd_data <= #1 14'd4992; + 8'd252 : rd_data <= #1 14'd5319; + 8'd253 : rd_data <= #1 14'd5623; + 8'd254 : rd_data <= #1 14'd4741; + 8'd255 : rd_data <= #1 14'd5044; + endcase // case(rd_addr) + end //if (strobe) + assign out_data[13:0]=reg_quadrant?-rd_data:rd_data; + sign_extend #(14,18) + ext_output (.in(out_data),.out(ext_out_data)); + +endmodule // rrc_coeff_ram_generated_0 + +//bw= 16 data_size= 5 abs_max= 32767 len= 16 +module rrc_coeff_ram_generated1_1 (input clock, input strobe, input [3:0] phase, input [4:0] in_data, output [15:0] out_data,output [17:0] ext_out_data); + +reg reg_quadrant; +wire quadrant=in_data[4]; +wire [7:0] rd_addr={phase,quadrant?~in_data[3:0]:in_data[3:0]}; +reg [15:0] rd_data; + + always @(posedge clock) + if (strobe) + begin + reg_quadrant <= #1 quadrant; + case (rd_addr) + 8'd0 : rd_data <= #1 -16'd23961; + 8'd1 : rd_data <= #1 16'd26300; + 8'd2 : rd_data <= #1 -16'd27846; + 8'd3 : rd_data <= #1 16'd22415; + 8'd4 : rd_data <= #1 -16'd21341; + 8'd5 : rd_data <= #1 16'd28920; + 8'd6 : rd_data <= #1 -16'd25226; + 8'd7 : rd_data <= #1 16'd25035; + 8'd8 : rd_data <= #1 -16'd25129; + 8'd9 : rd_data <= #1 16'd25132; + 8'd10 : rd_data <= #1 -16'd29014; + 8'd11 : rd_data <= #1 16'd21247; + 8'd12 : rd_data <= #1 -16'd22509; + 8'd13 : rd_data <= #1 16'd27753; + 8'd14 : rd_data <= #1 -16'd26394; + 8'd15 : rd_data <= #1 16'd23868; + 8'd16 : rd_data <= #1 -16'd24683; + 8'd17 : rd_data <= #1 -16'd6215; + 8'd18 : rd_data <= #1 16'd12020; + 8'd19 : rd_data <= #1 16'd30488; + 8'd20 : rd_data <= #1 -16'd32767; + 8'd21 : rd_data <= #1 -16'd14300; + 8'd22 : rd_data <= #1 16'd3936; + 8'd23 : rd_data <= #1 16'd22404; + 8'd24 : rd_data <= #1 -16'd22456; + 8'd25 : rd_data <= #1 -16'd3989; + 8'd26 : rd_data <= #1 16'd14247; + 8'd27 : rd_data <= #1 16'd32714; + 8'd28 : rd_data <= #1 -16'd30540; + 8'd29 : rd_data <= #1 -16'd12073; + 8'd30 : rd_data <= #1 16'd6163; + 8'd31 : rd_data <= #1 16'd24630; + 8'd32 : rd_data <= #1 -16'd26159; + 8'd33 : rd_data <= #1 16'd17748; + 8'd34 : rd_data <= #1 -16'd16669; + 8'd35 : rd_data <= #1 16'd27238; + 8'd36 : rd_data <= #1 -16'd27172; + 8'd37 : rd_data <= #1 16'd16736; + 8'd38 : rd_data <= #1 -16'd17682; + 8'd39 : rd_data <= #1 16'd26226; + 8'd40 : rd_data <= #1 -16'd26837; + 8'd41 : rd_data <= #1 16'd17070; + 8'd42 : rd_data <= #1 -16'd17347; + 8'd43 : rd_data <= #1 16'd26561; + 8'd44 : rd_data <= #1 -16'd27849; + 8'd45 : rd_data <= #1 16'd16058; + 8'd46 : rd_data <= #1 -16'd18359; + 8'd47 : rd_data <= #1 16'd25548; + 8'd48 : rd_data <= #1 -16'd22696; + 8'd49 : rd_data <= #1 -16'd20864; + 8'd50 : rd_data <= #1 16'd25925; + 8'd51 : rd_data <= #1 16'd27757; + 8'd52 : rd_data <= #1 -16'd30062; + 8'd53 : rd_data <= #1 -16'd28230; + 8'd54 : rd_data <= #1 16'd18560; + 8'd55 : rd_data <= #1 16'd20391; + 8'd56 : rd_data <= #1 -16'd19495; + 8'd57 : rd_data <= #1 -16'd17663; + 8'd58 : rd_data <= #1 16'd29126; + 8'd59 : rd_data <= #1 16'd30958; + 8'd60 : rd_data <= #1 -16'd26861; + 8'd61 : rd_data <= #1 -16'd25029; + 8'd62 : rd_data <= #1 16'd21761; + 8'd63 : rd_data <= #1 16'd23592; + 8'd64 : rd_data <= #1 -16'd25588; + 8'd65 : rd_data <= #1 16'd2293; + 8'd66 : rd_data <= #1 16'd2293; + 8'd67 : rd_data <= #1 16'd30174; + 8'd68 : rd_data <= #1 -16'd31788; + 8'd69 : rd_data <= #1 -16'd3907; + 8'd70 : rd_data <= #1 -16'd3907; + 8'd71 : rd_data <= #1 16'd23974; + 8'd72 : rd_data <= #1 -16'd24413; + 8'd73 : rd_data <= #1 16'd3468; + 8'd74 : rd_data <= #1 16'd3468; + 8'd75 : rd_data <= #1 16'd31349; + 8'd76 : rd_data <= #1 -16'd30613; + 8'd77 : rd_data <= #1 -16'd2732; + 8'd78 : rd_data <= #1 -16'd2732; + 8'd79 : rd_data <= #1 16'd25149; + 8'd80 : rd_data <= #1 -16'd25459; + 8'd81 : rd_data <= #1 16'd23162; + 8'd82 : rd_data <= #1 -16'd23628; + 8'd83 : rd_data <= #1 16'd24994; + 8'd84 : rd_data <= #1 -16'd24280; + 8'd85 : rd_data <= #1 16'd24341; + 8'd86 : rd_data <= #1 -16'd22449; + 8'd87 : rd_data <= #1 16'd26173; + 8'd88 : rd_data <= #1 -16'd26578; + 8'd89 : rd_data <= #1 16'd22044; + 8'd90 : rd_data <= #1 -16'd24746; + 8'd91 : rd_data <= #1 16'd23875; + 8'd92 : rd_data <= #1 -16'd25399; + 8'd93 : rd_data <= #1 16'd23222; + 8'd94 : rd_data <= #1 -16'd23567; + 8'd95 : rd_data <= #1 16'd25054; + 8'd96 : rd_data <= #1 -16'd23652; + 8'd97 : rd_data <= #1 -16'd14162; + 8'd98 : rd_data <= #1 16'd20256; + 8'd99 : rd_data <= #1 16'd29746; + 8'd100 : rd_data <= #1 -16'd32305; + 8'd101 : rd_data <= #1 -16'd22815; + 8'd102 : rd_data <= #1 16'd11602; + 8'd103 : rd_data <= #1 16'd21092; + 8'd104 : rd_data <= #1 -16'd20654; + 8'd105 : rd_data <= #1 -16'd11164; + 8'd106 : rd_data <= #1 16'd23253; + 8'd107 : rd_data <= #1 16'd32743; + 8'd108 : rd_data <= #1 -16'd29308; + 8'd109 : rd_data <= #1 -16'd19817; + 8'd110 : rd_data <= #1 16'd14600; + 8'd111 : rd_data <= #1 16'd24090; + 8'd112 : rd_data <= #1 -16'd26148; + 8'd113 : rd_data <= #1 16'd10555; + 8'd114 : rd_data <= #1 -16'd7681; + 8'd115 : rd_data <= #1 16'd29022; + 8'd116 : rd_data <= #1 -16'd29787; + 8'd117 : rd_data <= #1 16'd6917; + 8'd118 : rd_data <= #1 -16'd11319; + 8'd119 : rd_data <= #1 16'd25384; + 8'd120 : rd_data <= #1 -16'd26018; + 8'd121 : rd_data <= #1 16'd10685; + 8'd122 : rd_data <= #1 -16'd7550; + 8'd123 : rd_data <= #1 16'd29153; + 8'd124 : rd_data <= #1 -16'd29656; + 8'd125 : rd_data <= #1 16'd7047; + 8'd126 : rd_data <= #1 -16'd11189; + 8'd127 : rd_data <= #1 16'd25515; + 8'd128 : rd_data <= #1 -16'd23961; + 8'd129 : rd_data <= #1 16'd26300; + 8'd130 : rd_data <= #1 -16'd27846; + 8'd131 : rd_data <= #1 16'd22415; + 8'd132 : rd_data <= #1 -16'd21341; + 8'd133 : rd_data <= #1 16'd28920; + 8'd134 : rd_data <= #1 -16'd25226; + 8'd135 : rd_data <= #1 16'd25035; + 8'd136 : rd_data <= #1 -16'd25129; + 8'd137 : rd_data <= #1 16'd25132; + 8'd138 : rd_data <= #1 -16'd29014; + 8'd139 : rd_data <= #1 16'd21247; + 8'd140 : rd_data <= #1 -16'd22509; + 8'd141 : rd_data <= #1 16'd27753; + 8'd142 : rd_data <= #1 -16'd26394; + 8'd143 : rd_data <= #1 16'd23868; + 8'd144 : rd_data <= #1 -16'd24683; + 8'd145 : rd_data <= #1 -16'd6215; + 8'd146 : rd_data <= #1 16'd12020; + 8'd147 : rd_data <= #1 16'd30488; + 8'd148 : rd_data <= #1 -16'd32767; + 8'd149 : rd_data <= #1 -16'd14300; + 8'd150 : rd_data <= #1 16'd3936; + 8'd151 : rd_data <= #1 16'd22404; + 8'd152 : rd_data <= #1 -16'd22456; + 8'd153 : rd_data <= #1 -16'd3989; + 8'd154 : rd_data <= #1 16'd14247; + 8'd155 : rd_data <= #1 16'd32714; + 8'd156 : rd_data <= #1 -16'd30540; + 8'd157 : rd_data <= #1 -16'd12073; + 8'd158 : rd_data <= #1 16'd6163; + 8'd159 : rd_data <= #1 16'd24630; + 8'd160 : rd_data <= #1 -16'd26159; + 8'd161 : rd_data <= #1 16'd17748; + 8'd162 : rd_data <= #1 -16'd16669; + 8'd163 : rd_data <= #1 16'd27238; + 8'd164 : rd_data <= #1 -16'd27172; + 8'd165 : rd_data <= #1 16'd16736; + 8'd166 : rd_data <= #1 -16'd17682; + 8'd167 : rd_data <= #1 16'd26226; + 8'd168 : rd_data <= #1 -16'd26837; + 8'd169 : rd_data <= #1 16'd17070; + 8'd170 : rd_data <= #1 -16'd17347; + 8'd171 : rd_data <= #1 16'd26561; + 8'd172 : rd_data <= #1 -16'd27849; + 8'd173 : rd_data <= #1 16'd16058; + 8'd174 : rd_data <= #1 -16'd18359; + 8'd175 : rd_data <= #1 16'd25548; + 8'd176 : rd_data <= #1 -16'd22696; + 8'd177 : rd_data <= #1 -16'd20864; + 8'd178 : rd_data <= #1 16'd25925; + 8'd179 : rd_data <= #1 16'd27757; + 8'd180 : rd_data <= #1 -16'd30062; + 8'd181 : rd_data <= #1 -16'd28230; + 8'd182 : rd_data <= #1 16'd18560; + 8'd183 : rd_data <= #1 16'd20391; + 8'd184 : rd_data <= #1 -16'd19495; + 8'd185 : rd_data <= #1 -16'd17663; + 8'd186 : rd_data <= #1 16'd29126; + 8'd187 : rd_data <= #1 16'd30958; + 8'd188 : rd_data <= #1 -16'd26861; + 8'd189 : rd_data <= #1 -16'd25029; + 8'd190 : rd_data <= #1 16'd21761; + 8'd191 : rd_data <= #1 16'd23592; + 8'd192 : rd_data <= #1 -16'd25588; + 8'd193 : rd_data <= #1 16'd2293; + 8'd194 : rd_data <= #1 16'd2293; + 8'd195 : rd_data <= #1 16'd30174; + 8'd196 : rd_data <= #1 -16'd31788; + 8'd197 : rd_data <= #1 -16'd3907; + 8'd198 : rd_data <= #1 -16'd3907; + 8'd199 : rd_data <= #1 16'd23974; + 8'd200 : rd_data <= #1 -16'd24413; + 8'd201 : rd_data <= #1 16'd3468; + 8'd202 : rd_data <= #1 16'd3468; + 8'd203 : rd_data <= #1 16'd31349; + 8'd204 : rd_data <= #1 -16'd30613; + 8'd205 : rd_data <= #1 -16'd2732; + 8'd206 : rd_data <= #1 -16'd2732; + 8'd207 : rd_data <= #1 16'd25149; + 8'd208 : rd_data <= #1 -16'd25459; + 8'd209 : rd_data <= #1 16'd23162; + 8'd210 : rd_data <= #1 -16'd23628; + 8'd211 : rd_data <= #1 16'd24994; + 8'd212 : rd_data <= #1 -16'd24280; + 8'd213 : rd_data <= #1 16'd24341; + 8'd214 : rd_data <= #1 -16'd22449; + 8'd215 : rd_data <= #1 16'd26173; + 8'd216 : rd_data <= #1 -16'd26578; + 8'd217 : rd_data <= #1 16'd22044; + 8'd218 : rd_data <= #1 -16'd24746; + 8'd219 : rd_data <= #1 16'd23875; + 8'd220 : rd_data <= #1 -16'd25399; + 8'd221 : rd_data <= #1 16'd23222; + 8'd222 : rd_data <= #1 -16'd23567; + 8'd223 : rd_data <= #1 16'd25054; + 8'd224 : rd_data <= #1 -16'd23652; + 8'd225 : rd_data <= #1 -16'd14162; + 8'd226 : rd_data <= #1 16'd20256; + 8'd227 : rd_data <= #1 16'd29746; + 8'd228 : rd_data <= #1 -16'd32305; + 8'd229 : rd_data <= #1 -16'd22815; + 8'd230 : rd_data <= #1 16'd11602; + 8'd231 : rd_data <= #1 16'd21092; + 8'd232 : rd_data <= #1 -16'd20654; + 8'd233 : rd_data <= #1 -16'd11164; + 8'd234 : rd_data <= #1 16'd23253; + 8'd235 : rd_data <= #1 16'd32743; + 8'd236 : rd_data <= #1 -16'd29308; + 8'd237 : rd_data <= #1 -16'd19817; + 8'd238 : rd_data <= #1 16'd14600; + 8'd239 : rd_data <= #1 16'd24090; + 8'd240 : rd_data <= #1 -16'd26148; + 8'd241 : rd_data <= #1 16'd10555; + 8'd242 : rd_data <= #1 -16'd7681; + 8'd243 : rd_data <= #1 16'd29022; + 8'd244 : rd_data <= #1 -16'd29787; + 8'd245 : rd_data <= #1 16'd6917; + 8'd246 : rd_data <= #1 -16'd11319; + 8'd247 : rd_data <= #1 16'd25384; + 8'd248 : rd_data <= #1 -16'd26018; + 8'd249 : rd_data <= #1 16'd10685; + 8'd250 : rd_data <= #1 -16'd7550; + 8'd251 : rd_data <= #1 16'd29153; + 8'd252 : rd_data <= #1 -16'd29656; + 8'd253 : rd_data <= #1 16'd7047; + 8'd254 : rd_data <= #1 -16'd11189; + 8'd255 : rd_data <= #1 16'd25515; + endcase // case(rd_addr) + end //if (strobe) + assign out_data[15:0]=reg_quadrant?-rd_data:rd_data; + sign_extend #(16,18) + ext_output (.in(out_data),.out(ext_out_data)); + +endmodule // rrc_coeff_ram_generated_1 + +//bw= 10 data_size= 1 abs_max= 289 len= 1 +module rrc_coeff_ram_generated1_2 (input clock, input strobe, input [3:0] phase, input [0:0] in_data, output [9:0] out_data,output [17:0] ext_out_data); + +reg reg_quadrant; +wire quadrant=in_data[0]; +wire [3:0] rd_addr=phase; +reg [9:0] rd_data; + + always @(posedge clock) + if (strobe) + begin + reg_quadrant <= #1 quadrant; + case (rd_addr) + 4'd0 : rd_data <= #1 -10'd172; + 4'd1 : rd_data <= #1 10'd289; + 4'd2 : rd_data <= #1 10'd55; + 4'd3 : rd_data <= #1 10'd114; + 4'd4 : rd_data <= #1 10'd267; + 4'd5 : rd_data <= #1 -10'd73; + 4'd6 : rd_data <= #1 10'd236; + 4'd7 : rd_data <= #1 10'd179; + 4'd8 : rd_data <= #1 -10'd172; + 4'd9 : rd_data <= #1 10'd289; + 4'd10 : rd_data <= #1 10'd55; + 4'd11 : rd_data <= #1 10'd114; + 4'd12 : rd_data <= #1 10'd267; + 4'd13 : rd_data <= #1 -10'd73; + 4'd14 : rd_data <= #1 10'd236; + 4'd15 : rd_data <= #1 10'd179; + endcase // case(rd_addr) + end //if (strobe) + assign out_data[9:0]=reg_quadrant?-rd_data:rd_data; + sign_extend #(10,18) + ext_output (.in(out_data),.out(ext_out_data)); + +endmodule // rrc_coeff_ram_generated_2 + +//bw_memory [4, 4, 0] data_size 5 +module frac_interp_1 + + (input clock, input reset, input enable, + output reg strobe_in, input strobe_out, + input wire [4:0] tx_shift, + input wire [15:0] signal_in, + output reg [15:0] signal_out); + +reg [3:0] phase;//max 16 phases + +reg [3:0] in_count;//16 bits in every register + +reg [15:0] input_16; + +reg [15:0] shift_16_0; +wire get_bit= (phase==4'd1) || (phase==4'd3) || (phase==4'd4) || (phase==4'd6) || (phase==4'd7) || (phase==4'd9) || (phase==4'd11) || (phase==4'd12) || (phase==4'd14) || (phase==4'd15); + + always @(posedge clock) + if (reset) + begin + strobe_in <= #1 0;// Reset + in_count <=#1 0; + input_16 <= #1 0; + + shift_16_0 <= #1 0; + + end //if (reset) + else //if (reset) + begin + if(enable & strobe_out & get_bit & (in_count == 4'd15)) + strobe_in <=#1 1'd1;//Only works if output of previous stage is registered and only updates on this strobe_in + else // if(strobe_in) //input a new 16 bit word and shift all regs 16 bit to the right= to next register) + strobe_in <= #1 0;//notice the else is always executed, even if there is no strobe_out so strobe_in will only be high for 1 clock + + if (enable & strobe_out) + begin + if ( get_bit) + + begin //shift input 1 bit to the left + if(in_count == 4'd15) //(strobe_in) //if(in_count == 4'd0) + begin + //strobe_in <=#1 1'd1;//Only works if output of previous stage is registered and only updates on this strobe_in + input_16 <= #1 signal_in; + end //if(in_count == 4'd0) + else //if(in_count == 4'd0) + begin + input_16 <= #1 {1'd0,input_16[15:1]};//just shift right //MDVH 14feb2007 + //input_16 <= #1 {input_16[14:0],1'd0};//just shift left //MDVH 14feb2007 + end // if(in_count == 4'd0) else + //shift_16_0 <= #1 {shift_16_0[14:0],input_16[15]};//MDVH 14feb2007 + shift_16_0 <= #1 {input_16[0],shift_16_0[15:1]};//MDVH 14feb2007 + + + in_count <= #1 in_count+4'd1; + end //if ((phase==.... + end //if (enable & strobe_out) + end // if (reset) else + + always @(posedge clock) + if (reset) + phase <=#1 0; + else if (enable & strobe_out) + phase <=#1 phase + 4'd1;//phase will roll-over to zero and start again + + +wire [4:0] data_0; +wire [4:0] data_1; +wire [0:0] data_2; +assign data_2=shift_16_0[10:10]; +assign data_1=shift_16_0[9:5]; +assign data_0=shift_16_0[4:0]; +wire [17:0] sum_0; +wire [17:0] sum_1; +wire [17:0] sum_2; +wire [17:0] sum_3; +assign sum_3=0; +reg [17:0] sum_all; + +//wire [15:0] sum_all_16bit; + + rrc_coeff_ram_generated1_0 rrc_coeff_ram_0 ( .clock(clock),.strobe(strobe_out),.phase(phase),.in_data(data_0),.out_data(),.ext_out_data(sum_0) ); + rrc_coeff_ram_generated1_1 rrc_coeff_ram_1 ( .clock(clock),.strobe(strobe_out),.phase(phase),.in_data(data_1),.out_data(),.ext_out_data(sum_1) ); + rrc_coeff_ram_generated1_2 rrc_coeff_ram_2 ( .clock(clock),.strobe(strobe_out),.phase(phase),.in_data(data_2),.out_data(),.ext_out_data(sum_2) ); +//assign sum_all= sum_0 + sum_1 + sum_2; +reg [17:0] sum_01; +reg [17:0] sum_23; +reg [17:0] sum_0123; + + always @(posedge clock) + if (reset) + begin + + sum_01 <= #1 0; + sum_23 <= #1 0; + sum_0123 <= #1 0; + + sum_all <=#1 0; + signal_out <= #1 0; + end + else if (enable & strobe_out) + begin + + sum_01 <= #1 sum_0+sum_1; + sum_23 <= #1 sum_2+sum_3; + sum_0123 <= #1 sum_01+sum_23; + sum_all <= #1 sum_0123; + + case(tx_shift) + //5'd0 : signal_out <= #1 round_16(sum_all);//no gain reduce + 5'd0 : signal_out <= #1 { sum_all[16:1] + (sum_all[17] & ( sum_all[0] )) }; + 5'd1 : signal_out <= #1 { sum_all[17:2] + (sum_all[17] & (|sum_all[1:0])) }; + 5'd2 : signal_out <= #1 { {{(1){sum_all[17]}}, sum_all[17:3]} + (sum_all[17] & (|sum_all[2:0])) }; + 5'd3 : signal_out <= #1 { {{(2){sum_all[17]}}, sum_all[17:4]} + (sum_all[17] & (|sum_all[3:0])) }; + 5'd4 : signal_out <= #1 { {{(3){sum_all[17]}}, sum_all[17:5]} + (sum_all[17] & (|sum_all[4:0])) }; + 5'd5 : signal_out <= #1 { {{(4){sum_all[17]}}, sum_all[17:6]} + (sum_all[17] & (|sum_all[5:0])) }; + 5'd6 : signal_out <= #1 { {{(5){sum_all[17]}}, sum_all[17:7]} + (sum_all[17] & (|sum_all[6:0])) }; + 5'd7 : signal_out <= #1 { {{(6){sum_all[17]}}, sum_all[17:8]} + (sum_all[17] & (|sum_all[7:0])) }; + 5'd8 : signal_out <= #1 { {{(7){sum_all[17]}}, sum_all[17:9]} + (sum_all[17] & (|sum_all[8:0])) }; + 5'd9 : signal_out <= #1 { {{(8){sum_all[17]}}, sum_all[17:10]} + (sum_all[17] & (|sum_all[9:0])) }; + 5'd10 : signal_out <= #1 { {{(9){sum_all[17]}},sum_all[17:11]} + (sum_all[17] & (|sum_all[10:0]))}; + 5'd11 : signal_out <= #1 { {{(10){sum_all[17]}},sum_all[17:12]} + (sum_all[17] & (|sum_all[11:0]))}; + 5'd12 : signal_out <= #1 { {{(11){sum_all[17]}},sum_all[17:13]} + (sum_all[17] & (|sum_all[12:0]))}; + 5'd13 : signal_out <= #1 { {{(12){sum_all[17]}},sum_all[17:14]} + (sum_all[17] & (|sum_all[13:0]))}; + 5'd14 : signal_out <= #1 { {{(13){sum_all[17]}},sum_all[17:15]} + (sum_all[17] & (|sum_all[14:0]))}; + 5'd15 : signal_out <= #1 { {{(14){sum_all[17]}},sum_all[17:16]} + (sum_all[17] & (|sum_all[15:0]))}; + + -5'd1 : signal_out <= #1 {sum_all[15:0] }; + -5'd2 : signal_out <= #1 {sum_all[14:0] ,{(1){1'b0}}}; + -5'd3 : signal_out <= #1 {sum_all[13:0] ,{(2){1'b0}}}; + -5'd4 : signal_out <= #1 {sum_all[12:0] ,{(3){1'b0}}}; + -5'd5 : signal_out <= #1 {sum_all[11:0] ,{(4){1'b0}}}; + -5'd6 : signal_out <= #1 {sum_all[10:0] ,{(5){1'b0}}}; + -5'd7 : signal_out <= #1 {sum_all[9:0] ,{(6){1'b0}}}; + -5'd8 : signal_out <= #1 {sum_all[8:0] ,{(7){1'b0}}}; + -5'd9 : signal_out <= #1 {sum_all[7:0] ,{(8){1'b0}}}; + -5'd10 : signal_out <= #1 {sum_all[6:0] ,{(9){1'b0}}}; + -5'd11 : signal_out <= #1 {sum_all[5:0] ,{(10){1'b0}}}; + -5'd12 : signal_out <= #1 {sum_all[4:0] ,{(11){1'b0}}}; + -5'd13 : signal_out <= #1 {sum_all[3:0] ,{(12){1'b0}}}; + -5'd14 : signal_out <= #1 {sum_all[2:0] ,{(13){1'b0}}}; + -5'd15 : signal_out <= #1 {sum_all[1:0] ,{(14){1'b0}}}; + + default : signal_out <= #1 { sum_all[16:1] + (sum_all[17] & ( sum_all[0] )) }; + //signal_out <= #1 { sum_all[17:2] + (sum_all[17] & (|sum_all[1:0])) }; + endcase // case(shift) + + //sum_all_14bit <= #1 sum_0123[16:3] + (sum_0123[16] & |sum_0123[2:0]);//round to 14 bit (reduce gain by 2 bit = 12 dB) + + //signal_out <= #1 round_16(sum_all);//no gain reduce + //signal_out <= #1 {{(2){sum_all_14bit[13]}},sum_all_14bit};//sign_extend to 16 bit (gain reduced by 2 bit = 12 dB) + + end //else if (enable & strobe_out) + + +/*assign sum_all_16bit=round_16(sum_all); +//register the output to ease timing of the DDR DAC output + always @(posedge clock or posedge reset) + if (reset) + signal_out <= #1 0; // Reset + else + signal_out <= #1 sum_all_16bit; +*/ +//round to 16 bit +// function [15:0] round_16; +// input [16:0] in_val; +// round_16 = in_val[16:1] + (in_val[16] & |in_val[0]);//round_16 = in_val[16:1] + (in_val[16] & in_val[0]) +// endfunction // round_16 + + +endmodule //module frac_interp_1 Index: usrp/fpga/sdr_lib/generate_all_frac_interp_files.sh =================================================================== --- usrp/fpga/sdr_lib/generate_all_frac_interp_files.sh (revision 0) +++ usrp/fpga/sdr_lib/generate_all_frac_interp_files.sh (revision 0) @@ -0,0 +1,48 @@ +#!/bin/sh +# Generate code for Polyphase interpolating Root-Raised-Cosine filter with fractional interpolation factor" +# +# Copyright (C) 2007 Martin Dudok van Heel" +# +# This program is free software; you can redistribute it and/or modify" +# it under the terms of the GNU General Public License as published by" +# the Free Software Foundation; either version 2 of the License, or" +# (at your option) any later version." +# +# This program is distributed in the hope that it will be useful," +# but WITHOUT ANY WARRANTY; without even the implied warranty of" +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the" +# GNU General Public License for more details." +# +# You should have received a copy of the GNU General Public License" +# along with this program; if not, write to the Free Software" +# Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA" +# " +echo "Generating code for fractional interpolating Root-Raised_Cosine filters in verilog for USRP" +echo "Generating verilog files for both I and Q channels for alpha 0.2 and 0.35 and for 4 Mbit and 40 Mbit" +echo "*int16_dec10*.v are for 40 Mbit QPSK and *int16_dec1*.v are for 4 Mbit QPSK" +./generate_frac_interp_05nov2007.py -c 0 -d 10 -i 16 -a 0.35 >frac_interp_alpha0.35_int16_dec10_DACint4X_chan0.v +./generate_frac_interp_05nov2007.py -c 1 -d 10 -i 16 -a 0.35 >frac_interp_alpha0.35_int16_dec10_DACint4X_chan1.v +./generate_frac_interp_05nov2007.py -c 0 -d 1 -i 16 -a 0.35 >frac_interp_alpha0.35_int16_dec1_DACint4X_chan0.v +./generate_frac_interp_05nov2007.py -c 1 -d 1 -i 16 -a 0.35 >frac_interp_alpha0.35_int16_dec1_DACint4X_chan1.v +./generate_frac_interp_05nov2007.py -c 0 -d 10 -i 16 -a 0.2 >frac_interp_alpha0.2_int16_dec10_DACint4X_chan0.v +./generate_frac_interp_05nov2007.py -c 1 -d 10 -i 16 -a 0.2 >frac_interp_alpha0.2_int16_dec10_DACint4X_chan1.v +./generate_frac_interp_05nov2007.py -c 0 -d 1 -i 16 -a 0.2 >frac_interp_alpha0.2_int16_dec1_DACint4X_chan0.v +./generate_frac_interp_05nov2007.py -c 1 -d 1 -i 16 -a 0.2 >frac_interp_alpha0.2_int16_dec1_DACint4X_chan1.v +echo "done" +echo "For bitrate=40 Mbit/sec and alpha=0.35 use the following two files" +ls frac_interp_alpha0.35_int16_dec10_DACint4X_chan0.v +ls frac_interp_alpha0.35_int16_dec10_DACint4X_chan1.v +echo "For bitrate=4 Mbit/sec and alpha=0.35 use the following two files" +ls frac_interp_alpha0.35_int16_dec1_DACint4X_chan0.v +ls frac_interp_alpha0.35_int16_dec1_DACint4X_chan1.v +echo "For bitrate=40 Mbit/sec and alpha=0.2 use the following two files" +ls frac_interp_alpha0.2_int16_dec10_DACint4X_chan1.v +ls frac_interp_alpha0.2_int16_dec10_DACint4X_chan0.v +echo "For bitrate=4 Mbit/sec and alpha=0.2 use the following two files" +ls frac_interp_alpha0.2_int16_dec1_DACint4X_chan0.v +ls frac_interp_alpha0.2_int16_dec1_DACint4X_chan1.v +echo "Copy the two files to usrp/fpga/sdr_lib/frac_interp_0.v and frac_interp_1.v" +echo "After copying the two files, build the rbf file with the Altera Quartus II software." +echo "Make sure you use this special patched usrp sourcetree for usrp_qpsk. At the moment the standard usrp sourctree doesn't know about these files" +echo "Written by Martin Dudok van Heel, 2007" +echo "Olifantasia" Property changes on: usrp/fpga/sdr_lib/generate_all_frac_interp_files.sh ___________________________________________________________________ Name: svn:executable + * Index: usrp/fpga/sdr_lib/frac_interp_alpha0.2_int16_dec1_DACint4X_chan0.v =================================================================== --- usrp/fpga/sdr_lib/frac_interp_alpha0.2_int16_dec1_DACint4X_chan0.v (revision 0) +++ usrp/fpga/sdr_lib/frac_interp_alpha0.2_int16_dec1_DACint4X_chan0.v (revision 0) @@ -0,0 +1,879 @@ +// -*- verilog -*- +// +// Polyphase interpolating Root-Raised-Cosine filter +// +// Copyright (C) 2007 Martin Dudok van Heel +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// +// Polyphase interpolating Root-Raised-Cosine filter +// Interpolation ratio can be fractional (float) +// +// This file was generated by ./generate_frac_interp_05nov2007.py at 2007-11-08 00:15:23.496063 +// Written by Martin Dudok van Heel, 2007 +// Olifantasia +// +// Contact: http://www.olifantasia.com/gnuradio/contact.gif or nldudok1_olifantasia_com +// http://www.olifantasia.com +// +// This file can be used to build a special purpose firmware for the USRP +// USRP = Universal Software Radio Peripheral +// This special purpose firmware in combination with the GnuRadio framework can be used to create a high speed QPSK transmitter +// Depending on the decimation and interpolation factors used, the symbolrate can be from 2 to 20 Msymbols/sec +// The corresponding QPSK bitrate is 4 to 40 Mbit/sec +// alpha= 0.2 +// interpolation = 16.0 decimation= 1.0 interp_ratio= 16.0 decim_ratio= 0.0625 +// symbol rate = 2.0 Msymbol/sec +// QPSK bitrate = 4.0 Mbit/sec +// +//fractional ntaps 176.0 +//ntaps_per_filter= 11 +//nfilters= 16 +// s f incr d_mu ii oo step +// 0.0 0.0 0 0.0 0 0 0 +// 0.0625 0.0 0 0.0625 0 1 1 +// 0.125 0.0 0 0.125 0 2 2 +// 0.1875 0.0 0 0.1875 0 3 3 +// 0.25 0.0 0 0.25 0 4 4 +// 0.3125 0.0 0 0.3125 0 5 5 +// 0.375 0.0 0 0.375 0 6 6 +// 0.4375 0.0 0 0.4375 0 7 7 +// 0.5 0.0 0 0.5 0 8 8 +// 0.5625 0.0 0 0.5625 0 9 9 +// 0.625 0.0 0 0.625 0 10 10 +// 0.6875 0.0 0 0.6875 0 11 11 +// 0.75 0.0 0 0.75 0 12 12 +// 0.8125 0.0 0 0.8125 0 13 13 +// 0.875 0.0 0 0.875 0 14 14 +// 0.9375 0.0 0 0.9375 0 15 15 +//poly_filter[ 0 ] = +// [0.012276425742768845, -0.038158391642386949, 0.085383935692877666, -0.18582413547513857, 0.63081172819063314, 0.63081172819063314, -0.18582413547513857, 0.085383935692877666, -0.038158391642386949, 0.012276425742768845, 0.0012956563853800855] + +//poly_filter[ 1 ] = +// [0.0067053771043863149, -0.029085429385636123, 0.071671349627165801, -0.16311478744344357, 0.53715256029912584, 0.72022410284524896, -0.2022794687055513, 0.096208216988318704, -0.046097928986694008, 0.017677745052985291, -0.00180610413580281] + +//poly_filter[ 2 ] = +// [0.0012559063894013399, -0.01937724759416996, 0.055876818067479912, -0.13563705037865761, 0.4415692458117017, 0.80312255069339678, -0.21110075354176358, 0.1034075077591418, -0.052424552723671157, 0.022605592034878701, -0.0050465560383613026] + +//poly_filter[ 3 ] = +// [-0.0038066683095202003, -0.009526885008129744, 0.038838029990736031, -0.10492491909883139, 0.34636748878728713, 0.87736722339555218, -0.21106948651963514, 0.10635256340684114, -0.056702002655491461, 0.026758827510895762, -0.0082428187572101876] + +//poly_filter[ 4 ] = +// [-0.0082545095695661427, -7.8442979524903853e-17, 0.021386683884785231, -0.072504418238962198, 0.25376546383636761, 0.94101409093054489, -0.20118115883049581, 0.10455712121450497, -0.058561260885315596, 0.029854760451337354, -0.011202548701554096] + +//poly_filter[ 5 ] = +// [-0.011906242787328066, 0.008784760620874894, 0.0043136753630191298, -0.03984021212753959, 0.16582754988015289, 0.99237777483437095, -0.18069212746120333, 0.097709581878410862, -0.057722904308102688, 0.031645038861781369, -0.013734083296364351] + +//poly_filter[ 6 ] = +// [-0.014633125291013658, 0.016472060654605696, -0.011661896419860861, -0.008287046730187651, 0.08440464362663419, 1.030086410667886, -0.14915892799523031, 0.085699289017275276, -0.054016648119989123, 0.031930786250895349, -0.015657121608968226] + +//poly_filter[ 7 ] = +// [-0.016362250481865851, 0.022782281431648729, -0.025918813807834871, 0.020952344718333821, 0.011083035327064632, 1.053126546814495, -0.10646830143563842, 0.068636022936419336, -0.047397002279798629, 0.030576177554778709, -0.016813399068332405] + +//poly_filter[ 8 ] = +// [-0.017076787138575533, 0.027519682858549145, -0.037954085517163318, 0.046861549214532013, -0.052856519112105753, 1.0608764424006163, -0.052856519112105753, 0.046861549214532013, -0.037954085517163318, 0.027519682858549145, -0.017076787138575533] + +//poly_filter[ 9 ] = +// [-0.016813399068332405, 0.030576177554778709, -0.047397002279798629, 0.068636022936419336, -0.10646830143563842, 1.053126546814495, 0.011083035327064632, 0.020952344718333821, -0.025918813807834871, 0.022782281431648729, -0.016362250481865851] + +//poly_filter[ 10 ] = +// [-0.015657121608968226, 0.031930786250895349, -0.054016648119989123, 0.085699289017275276, -0.14915892799523031, 1.030086410667886, 0.08440464362663419, -0.008287046730187651, -0.011661896419860861, 0.016472060654605696, -0.014633125291013658] + +//poly_filter[ 11 ] = +// [-0.013734083296364351, 0.031645038861781369, -0.057722904308102688, 0.097709581878410862, -0.18069212746120333, 0.99237777483437095, 0.16582754988015289, -0.03984021212753959, 0.0043136753630191298, 0.008784760620874894, -0.011906242787328066] + +//poly_filter[ 12 ] = +// [-0.011202548701554096, 0.029854760451337354, -0.058561260885315596, 0.10455712121450497, -0.20118115883049581, 0.94101409093054489, 0.25376546383636761, -0.072504418238962198, 0.021386683884785231, -7.8442979524903853e-17, -0.0082545095695661427] + +//poly_filter[ 13 ] = +// [-0.0082428187572101876, 0.026758827510895762, -0.056702002655491461, 0.10635256340684114, -0.21106948651963514, 0.87736722339555218, 0.34636748878728713, -0.10492491909883139, 0.038838029990736031, -0.009526885008129744, -0.0038066683095202003] + +//poly_filter[ 14 ] = +// [-0.0050465560383613026, 0.022605592034878701, -0.052424552723671157, 0.1034075077591418, -0.21110075354176358, 0.80312255069339678, 0.4415692458117017, -0.13563705037865761, 0.055876818067479912, -0.01937724759416996, 0.0012559063894013399] + +//poly_filter[ 15 ] = +// [-0.00180610413580281, 0.017677745052985291, -0.046097928986694008, 0.096208216988318704, -0.2022794687055513, 0.72022410284524896, 0.53715256029912584, -0.16311478744344357, 0.071671349627165801, -0.029085429385636123, 0.0067053771043863149] + +// total_ntaps= 176 +// ntaps_per_filter= 11 +// nfilters= 16 +// filter resolution= 16 bits +// +//data_size= 5 phase_size= 4 +//abs_max= 1.5212482296 abs_max_16bit= 32767 signed_max_16bit= 32767 signed_min_16bit= -31514 +//nmemories= 3 +//incr_list = [15] +//bw= 16 data_size= 5 abs_max= 20515 len= 16 +module rrc_coeff_ram_generated0_0 (input clock, input strobe, input [3:0] phase, input [4:0] in_data, output [15:0] out_data,output [17:0] ext_out_data); + +reg reg_quadrant; +wire quadrant=in_data[4]; +wire [7:0] rd_addr={phase,quadrant?~in_data[3:0]:in_data[3:0]}; +reg [15:0] rd_data; + + always @(posedge clock) + if (strobe) + begin + reg_quadrant <= #1 quadrant; + case (rd_addr) + 8'd0 : rd_data <= #1 -16'd10866; + 8'd1 : rd_data <= #1 -16'd10338; + 8'd2 : rd_data <= #1 -16'd12510; + 8'd3 : rd_data <= #1 -16'd11981; + 8'd4 : rd_data <= #1 -16'd7188; + 8'd5 : rd_data <= #1 -16'd6659; + 8'd6 : rd_data <= #1 -16'd8832; + 8'd7 : rd_data <= #1 -16'd8303; + 8'd8 : rd_data <= #1 -16'd18872; + 8'd9 : rd_data <= #1 -16'd18343; + 8'd10 : rd_data <= #1 -16'd20515; + 8'd11 : rd_data <= #1 -16'd19987; + 8'd12 : rd_data <= #1 -16'd15193; + 8'd13 : rd_data <= #1 -16'd14664; + 8'd14 : rd_data <= #1 -16'd16837; + 8'd15 : rd_data <= #1 -16'd16308; + 8'd16 : rd_data <= #1 -16'd9118; + 8'd17 : rd_data <= #1 -16'd8829; + 8'd18 : rd_data <= #1 -16'd10371; + 8'd19 : rd_data <= #1 -16'd10082; + 8'd20 : rd_data <= #1 -16'd6031; + 8'd21 : rd_data <= #1 -16'd5742; + 8'd22 : rd_data <= #1 -16'd7284; + 8'd23 : rd_data <= #1 -16'd6995; + 8'd24 : rd_data <= #1 -16'd16145; + 8'd25 : rd_data <= #1 -16'd15856; + 8'd26 : rd_data <= #1 -16'd17398; + 8'd27 : rd_data <= #1 -16'd17109; + 8'd28 : rd_data <= #1 -16'd13058; + 8'd29 : rd_data <= #1 -16'd12769; + 8'd30 : rd_data <= #1 -16'd14311; + 8'd31 : rd_data <= #1 -16'd14022; + 8'd32 : rd_data <= #1 -16'd7403; + 8'd33 : rd_data <= #1 -16'd7349; + 8'd34 : rd_data <= #1 -16'd8238; + 8'd35 : rd_data <= #1 -16'd8184; + 8'd36 : rd_data <= #1 -16'd4996; + 8'd37 : rd_data <= #1 -16'd4942; + 8'd38 : rd_data <= #1 -16'd5831; + 8'd39 : rd_data <= #1 -16'd5776; + 8'd40 : rd_data <= #1 -16'd13246; + 8'd41 : rd_data <= #1 -16'd13192; + 8'd42 : rd_data <= #1 -16'd14081; + 8'd43 : rd_data <= #1 -16'd14027; + 8'd44 : rd_data <= #1 -16'd10839; + 8'd45 : rd_data <= #1 -16'd10785; + 8'd46 : rd_data <= #1 -16'd11674; + 8'd47 : rd_data <= #1 -16'd11620; + 8'd48 : rd_data <= #1 -16'd5750; + 8'd49 : rd_data <= #1 -16'd5914; + 8'd50 : rd_data <= #1 -16'd6160; + 8'd51 : rd_data <= #1 -16'd6324; + 8'd52 : rd_data <= #1 -16'd4077; + 8'd53 : rd_data <= #1 -16'd4241; + 8'd54 : rd_data <= #1 -16'd4487; + 8'd55 : rd_data <= #1 -16'd4651; + 8'd56 : rd_data <= #1 -16'd10270; + 8'd57 : rd_data <= #1 -16'd10434; + 8'd58 : rd_data <= #1 -16'd10680; + 8'd59 : rd_data <= #1 -16'd10844; + 8'd60 : rd_data <= #1 -16'd8597; + 8'd61 : rd_data <= #1 -16'd8761; + 8'd62 : rd_data <= #1 -16'd9007; + 8'd63 : rd_data <= #1 -16'd9171; + 8'd64 : rd_data <= #1 -16'd4187; + 8'd65 : rd_data <= #1 -16'd4543; + 8'd66 : rd_data <= #1 -16'd4187; + 8'd67 : rd_data <= #1 -16'd4543; + 8'd68 : rd_data <= #1 -16'd3266; + 8'd69 : rd_data <= #1 -16'd3621; + 8'd70 : rd_data <= #1 -16'd3266; + 8'd71 : rd_data <= #1 -16'd3621; + 8'd72 : rd_data <= #1 -16'd7311; + 8'd73 : rd_data <= #1 -16'd7666; + 8'd74 : rd_data <= #1 -16'd7311; + 8'd75 : rd_data <= #1 -16'd7666; + 8'd76 : rd_data <= #1 -16'd6389; + 8'd77 : rd_data <= #1 -16'd6745; + 8'd78 : rd_data <= #1 -16'd6389; + 8'd79 : rd_data <= #1 -16'd6745; + 8'd80 : rd_data <= #1 -16'd2739; + 8'd81 : rd_data <= #1 -16'd3252; + 8'd82 : rd_data <= #1 -16'd2361; + 8'd83 : rd_data <= #1 -16'd2874; + 8'd84 : rd_data <= #1 -16'd2554; + 8'd85 : rd_data <= #1 -16'd3066; + 8'd86 : rd_data <= #1 -16'd2175; + 8'd87 : rd_data <= #1 -16'd2688; + 8'd88 : rd_data <= #1 -16'd4456; + 8'd89 : rd_data <= #1 -16'd4969; + 8'd90 : rd_data <= #1 -16'd4077; + 8'd91 : rd_data <= #1 -16'd4590; + 8'd92 : rd_data <= #1 -16'd4270; + 8'd93 : rd_data <= #1 -16'd4783; + 8'd94 : rd_data <= #1 -16'd3891; + 8'd95 : rd_data <= #1 -16'd4404; + 8'd96 : rd_data <= #1 -16'd1428; + 8'd97 : rd_data <= #1 -16'd2058; + 8'd98 : rd_data <= #1 -16'd718; + 8'd99 : rd_data <= #1 -16'd1349; + 8'd100 : rd_data <= #1 -16'd1930; + 8'd101 : rd_data <= #1 -16'd2561; + 8'd102 : rd_data <= #1 -16'd1221; + 8'd103 : rd_data <= #1 -16'd1851; + 8'd104 : rd_data <= #1 -16'd1785; + 8'd105 : rd_data <= #1 -16'd2415; + 8'd106 : rd_data <= #1 -16'd1075; + 8'd107 : rd_data <= #1 -16'd1706; + 8'd108 : rd_data <= #1 -16'd2287; + 8'd109 : rd_data <= #1 -16'd2918; + 8'd110 : rd_data <= #1 -16'd1578; + 8'd111 : rd_data <= #1 -16'd2208; + 8'd112 : rd_data <= #1 -16'd270; + 8'd113 : rd_data <= #1 -16'd975; + 8'd114 : rd_data <= #1 16'd711; + 8'd115 : rd_data <= #1 16'd7; + 8'd116 : rd_data <= #1 -16'd1387; + 8'd117 : rd_data <= #1 -16'd2091; + 8'd118 : rd_data <= #1 -16'd405; + 8'd119 : rd_data <= #1 -16'd1110; + 8'd120 : rd_data <= #1 16'd633; + 8'd121 : rd_data <= #1 -16'd72; + 8'd122 : rd_data <= #1 16'd1614; + 8'd123 : rd_data <= #1 16'd909; + 8'd124 : rd_data <= #1 -16'd484; + 8'd125 : rd_data <= #1 -16'd1189; + 8'd126 : rd_data <= #1 16'd497; + 8'd127 : rd_data <= #1 -16'd207; + 8'd128 : rd_data <= #1 16'd722; + 8'd129 : rd_data <= #1 -16'd14; + 8'd130 : rd_data <= #1 16'd1907; + 8'd131 : rd_data <= #1 16'd1172; + 8'd132 : rd_data <= #1 -16'd913; + 8'd133 : rd_data <= #1 -16'd1649; + 8'd134 : rd_data <= #1 16'd272; + 8'd135 : rd_data <= #1 -16'd463; + 8'd136 : rd_data <= #1 16'd2740; + 8'd137 : rd_data <= #1 16'd2005; + 8'd138 : rd_data <= #1 16'd3926; + 8'd139 : rd_data <= #1 16'd3190; + 8'd140 : rd_data <= #1 16'd1105; + 8'd141 : rd_data <= #1 16'd370; + 8'd142 : rd_data <= #1 16'd2291; + 8'd143 : rd_data <= #1 16'd1555; + 8'd144 : rd_data <= #1 16'd1539; + 8'd145 : rd_data <= #1 16'd815; + 8'd146 : rd_data <= #1 16'd2857; + 8'd147 : rd_data <= #1 16'd2132; + 8'd148 : rd_data <= #1 -16'd502; + 8'd149 : rd_data <= #1 -16'd1227; + 8'd150 : rd_data <= #1 16'd815; + 8'd151 : rd_data <= #1 16'd90; + 8'd152 : rd_data <= #1 16'd4496; + 8'd153 : rd_data <= #1 16'd3772; + 8'd154 : rd_data <= #1 16'd5813; + 8'd155 : rd_data <= #1 16'd5089; + 8'd156 : rd_data <= #1 16'd2454; + 8'd157 : rd_data <= #1 16'd1730; + 8'd158 : rd_data <= #1 16'd3772; + 8'd159 : rd_data <= #1 16'd3047; + 8'd160 : rd_data <= #1 16'd2180; + 8'd161 : rd_data <= #1 16'd1505; + 8'd162 : rd_data <= #1 16'd3555; + 8'd163 : rd_data <= #1 16'd2881; + 8'd164 : rd_data <= #1 -16'd147; + 8'd165 : rd_data <= #1 -16'd822; + 8'd166 : rd_data <= #1 16'd1228; + 8'd167 : rd_data <= #1 16'd554; + 8'd168 : rd_data <= #1 16'd5872; + 8'd169 : rd_data <= #1 16'd5197; + 8'd170 : rd_data <= #1 16'd7247; + 8'd171 : rd_data <= #1 16'd6573; + 8'd172 : rd_data <= #1 16'd3545; + 8'd173 : rd_data <= #1 16'd2870; + 8'd174 : rd_data <= #1 16'd4920; + 8'd175 : rd_data <= #1 16'd4246; + 8'd176 : rd_data <= #1 16'd2645; + 8'd177 : rd_data <= #1 16'd2053; + 8'd178 : rd_data <= #1 16'd4008; + 8'd179 : rd_data <= #1 16'd3417; + 8'd180 : rd_data <= #1 16'd158; + 8'd181 : rd_data <= #1 -16'd433; + 8'd182 : rd_data <= #1 16'd1522; + 8'd183 : rd_data <= #1 16'd930; + 8'd184 : rd_data <= #1 16'd6854; + 8'd185 : rd_data <= #1 16'd6263; + 8'd186 : rd_data <= #1 16'd8217; + 8'd187 : rd_data <= #1 16'd7626; + 8'd188 : rd_data <= #1 16'd4368; + 8'd189 : rd_data <= #1 16'd3776; + 8'd190 : rd_data <= #1 16'd5731; + 8'd191 : rd_data <= #1 16'd5139; + 8'd192 : rd_data <= #1 16'd2941; + 8'd193 : rd_data <= #1 16'd2458; + 8'd194 : rd_data <= #1 16'd4227; + 8'd195 : rd_data <= #1 16'd3744; + 8'd196 : rd_data <= #1 16'd418; + 8'd197 : rd_data <= #1 -16'd65; + 8'd198 : rd_data <= #1 16'd1704; + 8'd199 : rd_data <= #1 16'd1222; + 8'd200 : rd_data <= #1 16'd7445; + 8'd201 : rd_data <= #1 16'd6962; + 8'd202 : rd_data <= #1 16'd8731; + 8'd203 : rd_data <= #1 16'd8249; + 8'd204 : rd_data <= #1 16'd4922; + 8'd205 : rd_data <= #1 16'd4440; + 8'd206 : rd_data <= #1 16'd6208; + 8'd207 : rd_data <= #1 16'd5726; + 8'd208 : rd_data <= #1 16'd3078; + 8'd209 : rd_data <= #1 16'd2723; + 8'd210 : rd_data <= #1 16'd4231; + 8'd211 : rd_data <= #1 16'd3876; + 8'd212 : rd_data <= #1 16'd635; + 8'd213 : rd_data <= #1 16'd280; + 8'd214 : rd_data <= #1 16'd1788; + 8'd215 : rd_data <= #1 16'd1433; + 8'd216 : rd_data <= #1 16'd7660; + 8'd217 : rd_data <= #1 16'd7305; + 8'd218 : rd_data <= #1 16'd8812; + 8'd219 : rd_data <= #1 16'd8457; + 8'd220 : rd_data <= #1 16'd5217; + 8'd221 : rd_data <= #1 16'd4862; + 8'd222 : rd_data <= #1 16'd6370; + 8'd223 : rd_data <= #1 16'd6015; + 8'd224 : rd_data <= #1 16'd3071; + 8'd225 : rd_data <= #1 16'd2853; + 8'd226 : rd_data <= #1 16'd4044; + 8'd227 : rd_data <= #1 16'd3827; + 8'd228 : rd_data <= #1 16'd812; + 8'd229 : rd_data <= #1 16'd595; + 8'd230 : rd_data <= #1 16'd1786; + 8'd231 : rd_data <= #1 16'd1569; + 8'd232 : rd_data <= #1 16'd7525; + 8'd233 : rd_data <= #1 16'd7308; + 8'd234 : rd_data <= #1 16'd8499; + 8'd235 : rd_data <= #1 16'd8282; + 8'd236 : rd_data <= #1 16'd5267; + 8'd237 : rd_data <= #1 16'd5050; + 8'd238 : rd_data <= #1 16'd6241; + 8'd239 : rd_data <= #1 16'd6023; + 8'd240 : rd_data <= #1 16'd2936; + 8'd241 : rd_data <= #1 16'd2858; + 8'd242 : rd_data <= #1 16'd3697; + 8'd243 : rd_data <= #1 16'd3620; + 8'd244 : rd_data <= #1 16'd950; + 8'd245 : rd_data <= #1 16'd872; + 8'd246 : rd_data <= #1 16'd1711; + 8'd247 : rd_data <= #1 16'd1634; + 8'd248 : rd_data <= #1 16'd7080; + 8'd249 : rd_data <= #1 16'd7003; + 8'd250 : rd_data <= #1 16'd7842; + 8'd251 : rd_data <= #1 16'd7764; + 8'd252 : rd_data <= #1 16'd5094; + 8'd253 : rd_data <= #1 16'd5017; + 8'd254 : rd_data <= #1 16'd5856; + 8'd255 : rd_data <= #1 16'd5778; + endcase // case(rd_addr) + end //if (strobe) + assign out_data[15:0]=reg_quadrant?-rd_data:rd_data; + sign_extend #(16,18) + ext_output (.in(out_data),.out(ext_out_data)); + +endmodule // rrc_coeff_ram_generated_0 + +//bw= 16 data_size= 5 abs_max= 32767 len= 16 +module rrc_coeff_ram_generated0_1 (input clock, input strobe, input [3:0] phase, input [4:0] in_data, output [15:0] out_data,output [17:0] ext_out_data); + +reg reg_quadrant; +wire quadrant=in_data[4]; +wire [7:0] rd_addr={phase,quadrant?~in_data[3:0]:in_data[3:0]}; +reg [15:0] rd_data; + + always @(posedge clock) + if (strobe) + begin + reg_quadrant <= #1 quadrant; + case (rd_addr) + 8'd0 : rd_data <= #1 -16'd10866; + 8'd1 : rd_data <= #1 16'd16308; + 8'd2 : rd_data <= #1 -16'd18872; + 8'd3 : rd_data <= #1 16'd8303; + 8'd4 : rd_data <= #1 -16'd7188; + 8'd5 : rd_data <= #1 16'd19987; + 8'd6 : rd_data <= #1 -16'd15193; + 8'd7 : rd_data <= #1 16'd11981; + 8'd8 : rd_data <= #1 -16'd12510; + 8'd9 : rd_data <= #1 16'd14664; + 8'd10 : rd_data <= #1 -16'd20515; + 8'd11 : rd_data <= #1 16'd6659; + 8'd12 : rd_data <= #1 -16'd8832; + 8'd13 : rd_data <= #1 16'd18343; + 8'd14 : rd_data <= #1 -16'd16837; + 8'd15 : rd_data <= #1 16'd10338; + 8'd16 : rd_data <= #1 -16'd12616; + 8'd17 : rd_data <= #1 16'd18410; + 8'd18 : rd_data <= #1 -16'd21330; + 8'd19 : rd_data <= #1 16'd9696; + 8'd20 : rd_data <= #1 -16'd8472; + 8'd21 : rd_data <= #1 16'd22555; + 8'd22 : rd_data <= #1 -16'd17186; + 8'd23 : rd_data <= #1 16'd13841; + 8'd24 : rd_data <= #1 -16'd14602; + 8'd25 : rd_data <= #1 16'd16424; + 8'd26 : rd_data <= #1 -16'd23316; + 8'd27 : rd_data <= #1 16'd7710; + 8'd28 : rd_data <= #1 -16'd10458; + 8'd29 : rd_data <= #1 16'd20569; + 8'd30 : rd_data <= #1 -16'd19172; + 8'd31 : rd_data <= #1 16'd11855; + 8'd32 : rd_data <= #1 -16'd14337; + 8'd33 : rd_data <= #1 16'd20261; + 8'd34 : rd_data <= #1 -16'd23431; + 8'd35 : rd_data <= #1 16'd11167; + 8'd36 : rd_data <= #1 -16'd9882; + 8'd37 : rd_data <= #1 16'd24716; + 8'd38 : rd_data <= #1 -16'd18976; + 8'd39 : rd_data <= #1 16'd15622; + 8'd40 : rd_data <= #1 -16'd16595; + 8'd41 : rd_data <= #1 16'd18002; + 8'd42 : rd_data <= #1 -16'd25689; + 8'd43 : rd_data <= #1 16'd8908; + 8'd44 : rd_data <= #1 -16'd12141; + 8'd45 : rd_data <= #1 16'd22457; + 8'd46 : rd_data <= #1 -16'd21235; + 8'd47 : rd_data <= #1 16'd13363; + 8'd48 : rd_data <= #1 -16'd15998; + 8'd49 : rd_data <= #1 16'd21799; + 8'd50 : rd_data <= #1 -16'd25090; + 8'd51 : rd_data <= #1 16'd12706; + 8'd52 : rd_data <= #1 -16'd11416; + 8'd53 : rd_data <= #1 16'd26380; + 8'd54 : rd_data <= #1 -16'd20509; + 8'd55 : rd_data <= #1 16'd17288; + 8'd56 : rd_data <= #1 -16'd18440; + 8'd57 : rd_data <= #1 16'd19356; + 8'd58 : rd_data <= #1 -16'd27533; + 8'd59 : rd_data <= #1 16'd10263; + 8'd60 : rd_data <= #1 -16'd13859; + 8'd61 : rd_data <= #1 16'd23938; + 8'd62 : rd_data <= #1 -16'd22951; + 8'd63 : rd_data <= #1 16'd14845; + 8'd64 : rd_data <= #1 -16'd17569; + 8'd65 : rd_data <= #1 16'd22969; + 8'd66 : rd_data <= #1 -16'd26236; + 8'd67 : rd_data <= #1 16'd14302; + 8'd68 : rd_data <= #1 -16'd13065; + 8'd69 : rd_data <= #1 16'd27473; + 8'd70 : rd_data <= #1 -16'd21732; + 8'd71 : rd_data <= #1 16'd18806; + 8'd72 : rd_data <= #1 -16'd20092; + 8'd73 : rd_data <= #1 16'd20446; + 8'd74 : rd_data <= #1 -16'd28759; + 8'd75 : rd_data <= #1 16'd11779; + 8'd76 : rd_data <= #1 -16'd15588; + 8'd77 : rd_data <= #1 16'd24950; + 8'd78 : rd_data <= #1 -16'd24255; + 8'd79 : rd_data <= #1 16'd16283; + 8'd80 : rd_data <= #1 -16'd19026; + 8'd81 : rd_data <= #1 16'd23724; + 8'd82 : rd_data <= #1 -16'd26810; + 8'd83 : rd_data <= #1 16'd15940; + 8'd84 : rd_data <= #1 -16'd14817; + 8'd85 : rd_data <= #1 16'd27934; + 8'd86 : rd_data <= #1 -16'd22601; + 8'd87 : rd_data <= #1 16'd20150; + 8'd88 : rd_data <= #1 -16'd21513; + 8'd89 : rd_data <= #1 16'd21238; + 8'd90 : rd_data <= #1 -16'd29297; + 8'd91 : rd_data <= #1 16'd13454; + 8'd92 : rd_data <= #1 -16'd17304; + 8'd93 : rd_data <= #1 16'd25447; + 8'd94 : rd_data <= #1 -16'd25088; + 8'd95 : rd_data <= #1 16'd17663; + 8'd96 : rd_data <= #1 -16'd20345; + 8'd97 : rd_data <= #1 16'd24030; + 8'd98 : rd_data <= #1 -16'd26771; + 8'd99 : rd_data <= #1 16'd17605; + 8'd100 : rd_data <= #1 -16'd16653; + 8'd101 : rd_data <= #1 16'd27722; + 8'd102 : rd_data <= #1 -16'd23079; + 8'd103 : rd_data <= #1 16'd21296; + 8'd104 : rd_data <= #1 -16'd22672; + 8'd105 : rd_data <= #1 16'd21703; + 8'd106 : rd_data <= #1 -16'd29098; + 8'd107 : rd_data <= #1 16'd15278; + 8'd108 : rd_data <= #1 -16'd18980; + 8'd109 : rd_data <= #1 16'd25395; + 8'd110 : rd_data <= #1 -16'd25406; + 8'd111 : rd_data <= #1 16'd18969; + 8'd112 : rd_data <= #1 -16'd21507; + 8'd113 : rd_data <= #1 16'd23861; + 8'd114 : rd_data <= #1 -16'd26093; + 8'd115 : rd_data <= #1 16'd19275; + 8'd116 : rd_data <= #1 -16'd18550; + 8'd117 : rd_data <= #1 16'd26818; + 8'd118 : rd_data <= #1 -16'd23136; + 8'd119 : rd_data <= #1 16'd22231; + 8'd120 : rd_data <= #1 -16'd23548; + 8'd121 : rd_data <= #1 16'd21819; + 8'd122 : rd_data <= #1 -16'd28135; + 8'd123 : rd_data <= #1 16'd17233; + 8'd124 : rd_data <= #1 -16'd20592; + 8'd125 : rd_data <= #1 16'd24776; + 8'd126 : rd_data <= #1 -16'd25178; + 8'd127 : rd_data <= #1 16'd20189; + 8'd128 : rd_data <= #1 -16'd22497; + 8'd129 : rd_data <= #1 16'd23205; + 8'd130 : rd_data <= #1 -16'd24774; + 8'd131 : rd_data <= #1 16'd20928; + 8'd132 : rd_data <= #1 -16'd20478; + 8'd133 : rd_data <= #1 16'd25223; + 8'd134 : rd_data <= #1 -16'd22755; + 8'd135 : rd_data <= #1 16'd22946; + 8'd136 : rd_data <= #1 -16'd24132; + 8'd137 : rd_data <= #1 16'd21570; + 8'd138 : rd_data <= #1 -16'd26409; + 8'd139 : rd_data <= #1 16'd19293; + 8'd140 : rd_data <= #1 -16'd22113; + 8'd141 : rd_data <= #1 16'd23588; + 8'd142 : rd_data <= #1 -16'd24390; + 8'd143 : rd_data <= #1 16'd21311; + 8'd144 : rd_data <= #1 -16'd23306; + 8'd145 : rd_data <= #1 16'd22061; + 8'd146 : rd_data <= #1 -16'd22829; + 8'd147 : rd_data <= #1 16'd22539; + 8'd148 : rd_data <= #1 -16'd22404; + 8'd149 : rd_data <= #1 16'd22964; + 8'd150 : rd_data <= #1 -16'd21926; + 8'd151 : rd_data <= #1 16'd23441; + 8'd152 : rd_data <= #1 -16'd24423; + 8'd153 : rd_data <= #1 16'd20945; + 8'd154 : rd_data <= #1 -16'd23945; + 8'd155 : rd_data <= #1 16'd21422; + 8'd156 : rd_data <= #1 -16'd23520; + 8'd157 : rd_data <= #1 16'd21847; + 8'd158 : rd_data <= #1 -16'd23043; + 8'd159 : rd_data <= #1 16'd22325; + 8'd160 : rd_data <= #1 -16'd23931; + 8'd161 : rd_data <= #1 16'd20444; + 8'd162 : rd_data <= #1 -16'd20295; + 8'd163 : rd_data <= #1 16'd24081; + 8'd164 : rd_data <= #1 -16'd24288; + 8'd165 : rd_data <= #1 16'd20087; + 8'd166 : rd_data <= #1 -16'd20652; + 8'd167 : rd_data <= #1 16'd23724; + 8'd168 : rd_data <= #1 -16'd24433; + 8'd169 : rd_data <= #1 16'd19942; + 8'd170 : rd_data <= #1 -16'd20797; + 8'd171 : rd_data <= #1 16'd23578; + 8'd172 : rd_data <= #1 -16'd24790; + 8'd173 : rd_data <= #1 16'd19585; + 8'd174 : rd_data <= #1 -16'd21154; + 8'd175 : rd_data <= #1 16'd23221; + 8'd176 : rd_data <= #1 -16'd24371; + 8'd177 : rd_data <= #1 16'd18380; + 8'd178 : rd_data <= #1 -16'd17228; + 8'd179 : rd_data <= #1 16'd25523; + 8'd180 : rd_data <= #1 -16'd26087; + 8'd181 : rd_data <= #1 16'd16663; + 8'd182 : rd_data <= #1 -16'd18944; + 8'd183 : rd_data <= #1 16'd23807; + 8'd184 : rd_data <= #1 -16'd24185; + 8'd185 : rd_data <= #1 16'd18565; + 8'd186 : rd_data <= #1 -16'd17042; + 8'd187 : rd_data <= #1 16'd25709; + 8'd188 : rd_data <= #1 -16'd25902; + 8'd189 : rd_data <= #1 16'd16849; + 8'd190 : rd_data <= #1 -16'd18758; + 8'd191 : rd_data <= #1 16'd23993; + 8'd192 : rd_data <= #1 -16'd24634; + 8'd193 : rd_data <= #1 16'd15904; + 8'd194 : rd_data <= #1 -16'd13702; + 8'd195 : rd_data <= #1 16'd26836; + 8'd196 : rd_data <= #1 -16'd27757; + 8'd197 : rd_data <= #1 16'd12781; + 8'd198 : rd_data <= #1 -16'd16825; + 8'd199 : rd_data <= #1 16'd23713; + 8'd200 : rd_data <= #1 -16'd23713; + 8'd201 : rd_data <= #1 16'd16825; + 8'd202 : rd_data <= #1 -16'd12781; + 8'd203 : rd_data <= #1 16'd27757; + 8'd204 : rd_data <= #1 -16'd26836; + 8'd205 : rd_data <= #1 16'd13702; + 8'd206 : rd_data <= #1 -16'd15904; + 8'd207 : rd_data <= #1 16'd24634; + 8'd208 : rd_data <= #1 -16'd24730; + 8'd209 : rd_data <= #1 16'd13066; + 8'd210 : rd_data <= #1 -16'd9809; + 8'd211 : rd_data <= #1 16'd27987; + 8'd212 : rd_data <= #1 -16'd29250; + 8'd213 : rd_data <= #1 16'd8546; + 8'd214 : rd_data <= #1 -16'd14329; + 8'd215 : rd_data <= #1 16'd23467; + 8'd216 : rd_data <= #1 -16'd23057; + 8'd217 : rd_data <= #1 16'd14739; + 8'd218 : rd_data <= #1 -16'd8136; + 8'd219 : rd_data <= #1 16'd29660; + 8'd220 : rd_data <= #1 -16'd27577; + 8'd221 : rd_data <= #1 16'd10219; + 8'd222 : rd_data <= #1 -16'd12656; + 8'd223 : rd_data <= #1 16'd25140; + 8'd224 : rd_data <= #1 -16'd24675; + 8'd225 : rd_data <= #1 16'd9923; + 8'd226 : rd_data <= #1 -16'd5652; + 8'd227 : rd_data <= #1 16'd28945; + 8'd228 : rd_data <= #1 -16'd30518; + 8'd229 : rd_data <= #1 16'd4080; + 8'd230 : rd_data <= #1 -16'd11495; + 8'd231 : rd_data <= #1 16'd23102; + 8'd232 : rd_data <= #1 -16'd22268; + 8'd233 : rd_data <= #1 16'd12330; + 8'd234 : rd_data <= #1 -16'd3245; + 8'd235 : rd_data <= #1 16'd31353; + 8'd236 : rd_data <= #1 -16'd28111; + 8'd237 : rd_data <= #1 16'd6487; + 8'd238 : rd_data <= #1 -16'd9088; + 8'd239 : rd_data <= #1 16'd25509; + 8'd240 : rd_data <= #1 -16'd24487; + 8'd241 : rd_data <= #1 16'd6539; + 8'd242 : rd_data <= #1 -16'd1347; + 8'd243 : rd_data <= #1 16'd29679; + 8'd244 : rd_data <= #1 -16'd31514; + 8'd245 : rd_data <= #1 -16'd487; + 8'd246 : rd_data <= #1 -16'd8374; + 8'd247 : rd_data <= #1 16'd22653; + 8'd248 : rd_data <= #1 -16'd21400; + 8'd249 : rd_data <= #1 16'd9627; + 8'd250 : rd_data <= #1 16'd1740; + 8'd251 : rd_data <= #1 16'd32767; + 8'd252 : rd_data <= #1 -16'd28426; + 8'd253 : rd_data <= #1 16'd2600; + 8'd254 : rd_data <= #1 -16'd5286; + 8'd255 : rd_data <= #1 16'd25740; + endcase // case(rd_addr) + end //if (strobe) + assign out_data[15:0]=reg_quadrant?-rd_data:rd_data; + sign_extend #(16,18) + ext_output (.in(out_data),.out(ext_out_data)); + +endmodule // rrc_coeff_ram_generated_1 + +//bw= 10 data_size= 1 abs_max= 368 len= 1 +module rrc_coeff_ram_generated0_2 (input clock, input strobe, input [3:0] phase, input [0:0] in_data, output [9:0] out_data,output [17:0] ext_out_data); + +reg reg_quadrant; +wire quadrant=in_data[0]; +wire [3:0] rd_addr=phase; +reg [9:0] rd_data; + + always @(posedge clock) + if (strobe) + begin + reg_quadrant <= #1 quadrant; + case (rd_addr) + 4'd0 : rd_data <= #1 -10'd28; + 4'd1 : rd_data <= #1 10'd39; + 4'd2 : rd_data <= #1 10'd109; + 4'd3 : rd_data <= #1 10'd178; + 4'd4 : rd_data <= #1 10'd241; + 4'd5 : rd_data <= #1 10'd296; + 4'd6 : rd_data <= #1 10'd337; + 4'd7 : rd_data <= #1 10'd362; + 4'd8 : rd_data <= #1 10'd368; + 4'd9 : rd_data <= #1 10'd352; + 4'd10 : rd_data <= #1 10'd315; + 4'd11 : rd_data <= #1 10'd256; + 4'd12 : rd_data <= #1 10'd178; + 4'd13 : rd_data <= #1 10'd82; + 4'd14 : rd_data <= #1 -10'd27; + 4'd15 : rd_data <= #1 -10'd144; + endcase // case(rd_addr) + end //if (strobe) + assign out_data[9:0]=reg_quadrant?-rd_data:rd_data; + sign_extend #(10,18) + ext_output (.in(out_data),.out(ext_out_data)); + +endmodule // rrc_coeff_ram_generated_2 + +//bw_memory [4, 4, 0] data_size 5 +module frac_interp_0 + + (input clock, input reset, input enable, + output reg strobe_in, input strobe_out, + input wire [4:0] tx_shift, + input wire [15:0] signal_in, + output reg [15:0] signal_out); + +reg [3:0] phase;//max 16 phases + +reg [3:0] in_count;//16 bits in every register + +reg [15:0] input_16; + +reg [15:0] shift_16_0; +wire get_bit= (phase==4'd15); + + always @(posedge clock) + if (reset) + begin + strobe_in <= #1 0;// Reset + in_count <=#1 0; + input_16 <= #1 0; + + shift_16_0 <= #1 0; + + end //if (reset) + else //if (reset) + begin + if(enable & strobe_out & get_bit & (in_count == 4'd15)) + strobe_in <=#1 1'd1;//Only works if output of previous stage is registered and only updates on this strobe_in + else // if(strobe_in) //input a new 16 bit word and shift all regs 16 bit to the right= to next register) + strobe_in <= #1 0;//notice the else is always executed, even if there is no strobe_out so strobe_in will only be high for 1 clock + + if (enable & strobe_out) + begin + if ( get_bit) + + begin //shift input 1 bit to the left + if(in_count == 4'd15) //(strobe_in) //if(in_count == 4'd0) + begin + //strobe_in <=#1 1'd1;//Only works if output of previous stage is registered and only updates on this strobe_in + input_16 <= #1 signal_in; + end //if(in_count == 4'd0) + else //if(in_count == 4'd0) + begin + input_16 <= #1 {1'd0,input_16[15:1]};//just shift right //MDVH 14feb2007 + //input_16 <= #1 {input_16[14:0],1'd0};//just shift left //MDVH 14feb2007 + end // if(in_count == 4'd0) else + //shift_16_0 <= #1 {shift_16_0[14:0],input_16[15]};//MDVH 14feb2007 + shift_16_0 <= #1 {input_16[0],shift_16_0[15:1]};//MDVH 14feb2007 + + + in_count <= #1 in_count+4'd1; + end //if ((phase==.... + end //if (enable & strobe_out) + end // if (reset) else + + always @(posedge clock) + if (reset) + phase <=#1 0; + else if (enable & strobe_out) + phase <=#1 phase + 4'd1;//phase will roll-over to zero and start again + + +wire [4:0] data_0; +wire [4:0] data_1; +wire [0:0] data_2; +assign data_2=shift_16_0[10:10]; +assign data_1=shift_16_0[9:5]; +assign data_0=shift_16_0[4:0]; +wire [17:0] sum_0; +wire [17:0] sum_1; +wire [17:0] sum_2; +wire [17:0] sum_3; +assign sum_3=0; +reg [17:0] sum_all; + +//wire [15:0] sum_all_16bit; + + rrc_coeff_ram_generated0_0 rrc_coeff_ram_0 ( .clock(clock),.strobe(strobe_out),.phase(phase),.in_data(data_0),.out_data(),.ext_out_data(sum_0) ); + rrc_coeff_ram_generated0_1 rrc_coeff_ram_1 ( .clock(clock),.strobe(strobe_out),.phase(phase),.in_data(data_1),.out_data(),.ext_out_data(sum_1) ); + rrc_coeff_ram_generated0_2 rrc_coeff_ram_2 ( .clock(clock),.strobe(strobe_out),.phase(phase),.in_data(data_2),.out_data(),.ext_out_data(sum_2) ); +//assign sum_all= sum_0 + sum_1 + sum_2; +reg [17:0] sum_01; +reg [17:0] sum_23; +reg [17:0] sum_0123; + + always @(posedge clock) + if (reset) + begin + + sum_01 <= #1 0; + sum_23 <= #1 0; + sum_0123 <= #1 0; + + sum_all <=#1 0; + signal_out <= #1 0; + end + else if (enable & strobe_out) + begin + + sum_01 <= #1 sum_0+sum_1; + sum_23 <= #1 sum_2+sum_3; + sum_0123 <= #1 sum_01+sum_23; + sum_all <= #1 sum_0123; + + case(tx_shift) + //5'd0 : signal_out <= #1 round_16(sum_all);//no gain reduce + 5'd0 : signal_out <= #1 { sum_all[16:1] + (sum_all[17] & ( sum_all[0] )) }; + 5'd1 : signal_out <= #1 { sum_all[17:2] + (sum_all[17] & (|sum_all[1:0])) }; + 5'd2 : signal_out <= #1 { {{(1){sum_all[17]}}, sum_all[17:3]} + (sum_all[17] & (|sum_all[2:0])) }; + 5'd3 : signal_out <= #1 { {{(2){sum_all[17]}}, sum_all[17:4]} + (sum_all[17] & (|sum_all[3:0])) }; + 5'd4 : signal_out <= #1 { {{(3){sum_all[17]}}, sum_all[17:5]} + (sum_all[17] & (|sum_all[4:0])) }; + 5'd5 : signal_out <= #1 { {{(4){sum_all[17]}}, sum_all[17:6]} + (sum_all[17] & (|sum_all[5:0])) }; + 5'd6 : signal_out <= #1 { {{(5){sum_all[17]}}, sum_all[17:7]} + (sum_all[17] & (|sum_all[6:0])) }; + 5'd7 : signal_out <= #1 { {{(6){sum_all[17]}}, sum_all[17:8]} + (sum_all[17] & (|sum_all[7:0])) }; + 5'd8 : signal_out <= #1 { {{(7){sum_all[17]}}, sum_all[17:9]} + (sum_all[17] & (|sum_all[8:0])) }; + 5'd9 : signal_out <= #1 { {{(8){sum_all[17]}}, sum_all[17:10]} + (sum_all[17] & (|sum_all[9:0])) }; + 5'd10 : signal_out <= #1 { {{(9){sum_all[17]}},sum_all[17:11]} + (sum_all[17] & (|sum_all[10:0]))}; + 5'd11 : signal_out <= #1 { {{(10){sum_all[17]}},sum_all[17:12]} + (sum_all[17] & (|sum_all[11:0]))}; + 5'd12 : signal_out <= #1 { {{(11){sum_all[17]}},sum_all[17:13]} + (sum_all[17] & (|sum_all[12:0]))}; + 5'd13 : signal_out <= #1 { {{(12){sum_all[17]}},sum_all[17:14]} + (sum_all[17] & (|sum_all[13:0]))}; + 5'd14 : signal_out <= #1 { {{(13){sum_all[17]}},sum_all[17:15]} + (sum_all[17] & (|sum_all[14:0]))}; + 5'd15 : signal_out <= #1 { {{(14){sum_all[17]}},sum_all[17:16]} + (sum_all[17] & (|sum_all[15:0]))}; + + -5'd1 : signal_out <= #1 {sum_all[15:0] }; + -5'd2 : signal_out <= #1 {sum_all[14:0] ,{(1){1'b0}}}; + -5'd3 : signal_out <= #1 {sum_all[13:0] ,{(2){1'b0}}}; + -5'd4 : signal_out <= #1 {sum_all[12:0] ,{(3){1'b0}}}; + -5'd5 : signal_out <= #1 {sum_all[11:0] ,{(4){1'b0}}}; + -5'd6 : signal_out <= #1 {sum_all[10:0] ,{(5){1'b0}}}; + -5'd7 : signal_out <= #1 {sum_all[9:0] ,{(6){1'b0}}}; + -5'd8 : signal_out <= #1 {sum_all[8:0] ,{(7){1'b0}}}; + -5'd9 : signal_out <= #1 {sum_all[7:0] ,{(8){1'b0}}}; + -5'd10 : signal_out <= #1 {sum_all[6:0] ,{(9){1'b0}}}; + -5'd11 : signal_out <= #1 {sum_all[5:0] ,{(10){1'b0}}}; + -5'd12 : signal_out <= #1 {sum_all[4:0] ,{(11){1'b0}}}; + -5'd13 : signal_out <= #1 {sum_all[3:0] ,{(12){1'b0}}}; + -5'd14 : signal_out <= #1 {sum_all[2:0] ,{(13){1'b0}}}; + -5'd15 : signal_out <= #1 {sum_all[1:0] ,{(14){1'b0}}}; + + default : signal_out <= #1 { sum_all[16:1] + (sum_all[17] & ( sum_all[0] )) }; + //signal_out <= #1 { sum_all[17:2] + (sum_all[17] & (|sum_all[1:0])) }; + endcase // case(shift) + + //sum_all_14bit <= #1 sum_0123[16:3] + (sum_0123[16] & |sum_0123[2:0]);//round to 14 bit (reduce gain by 2 bit = 12 dB) + + //signal_out <= #1 round_16(sum_all);//no gain reduce + //signal_out <= #1 {{(2){sum_all_14bit[13]}},sum_all_14bit};//sign_extend to 16 bit (gain reduced by 2 bit = 12 dB) + + end //else if (enable & strobe_out) + + +/*assign sum_all_16bit=round_16(sum_all); +//register the output to ease timing of the DDR DAC output + always @(posedge clock or posedge reset) + if (reset) + signal_out <= #1 0; // Reset + else + signal_out <= #1 sum_all_16bit; +*/ +//round to 16 bit +// function [15:0] round_16; +// input [16:0] in_val; +// round_16 = in_val[16:1] + (in_val[16] & |in_val[0]);//round_16 = in_val[16:1] + (in_val[16] & in_val[0]) +// endfunction // round_16 + + +endmodule //module frac_interp_0 Index: usrp/fpga/sdr_lib/frac_interp_alpha0.2_int16_dec1_DACint4X_chan1.v =================================================================== --- usrp/fpga/sdr_lib/frac_interp_alpha0.2_int16_dec1_DACint4X_chan1.v (revision 0) +++ usrp/fpga/sdr_lib/frac_interp_alpha0.2_int16_dec1_DACint4X_chan1.v (revision 0) @@ -0,0 +1,879 @@ +// -*- verilog -*- +// +// Polyphase interpolating Root-Raised-Cosine filter +// +// Copyright (C) 2007 Martin Dudok van Heel +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// +// Polyphase interpolating Root-Raised-Cosine filter +// Interpolation ratio can be fractional (float) +// +// This file was generated by ./generate_frac_interp_05nov2007.py at 2007-11-08 00:15:23.694760 +// Written by Martin Dudok van Heel, 2007 +// Olifantasia +// +// Contact: http://www.olifantasia.com/gnuradio/contact.gif or nldudok1_olifantasia_com +// http://www.olifantasia.com +// +// This file can be used to build a special purpose firmware for the USRP +// USRP = Universal Software Radio Peripheral +// This special purpose firmware in combination with the GnuRadio framework can be used to create a high speed QPSK transmitter +// Depending on the decimation and interpolation factors used, the symbolrate can be from 2 to 20 Msymbols/sec +// The corresponding QPSK bitrate is 4 to 40 Mbit/sec +// alpha= 0.2 +// interpolation = 16.0 decimation= 1.0 interp_ratio= 16.0 decim_ratio= 0.0625 +// symbol rate = 2.0 Msymbol/sec +// QPSK bitrate = 4.0 Mbit/sec +// +//fractional ntaps 176.0 +//ntaps_per_filter= 11 +//nfilters= 16 +// s f incr d_mu ii oo step +// 0.0 0.0 0 0.0 0 0 0 +// 0.0625 0.0 0 0.0625 0 1 1 +// 0.125 0.0 0 0.125 0 2 2 +// 0.1875 0.0 0 0.1875 0 3 3 +// 0.25 0.0 0 0.25 0 4 4 +// 0.3125 0.0 0 0.3125 0 5 5 +// 0.375 0.0 0 0.375 0 6 6 +// 0.4375 0.0 0 0.4375 0 7 7 +// 0.5 0.0 0 0.5 0 8 8 +// 0.5625 0.0 0 0.5625 0 9 9 +// 0.625 0.0 0 0.625 0 10 10 +// 0.6875 0.0 0 0.6875 0 11 11 +// 0.75 0.0 0 0.75 0 12 12 +// 0.8125 0.0 0 0.8125 0 13 13 +// 0.875 0.0 0 0.875 0 14 14 +// 0.9375 0.0 0 0.9375 0 15 15 +//poly_filter[ 0 ] = +// [0.012276425742768845, -0.038158391642386949, 0.085383935692877666, -0.18582413547513857, 0.63081172819063314, 0.63081172819063314, -0.18582413547513857, 0.085383935692877666, -0.038158391642386949, 0.012276425742768845, 0.0012956563853800855] + +//poly_filter[ 1 ] = +// [0.0067053771043863149, -0.029085429385636123, 0.071671349627165801, -0.16311478744344357, 0.53715256029912584, 0.72022410284524896, -0.2022794687055513, 0.096208216988318704, -0.046097928986694008, 0.017677745052985291, -0.00180610413580281] + +//poly_filter[ 2 ] = +// [0.0012559063894013399, -0.01937724759416996, 0.055876818067479912, -0.13563705037865761, 0.4415692458117017, 0.80312255069339678, -0.21110075354176358, 0.1034075077591418, -0.052424552723671157, 0.022605592034878701, -0.0050465560383613026] + +//poly_filter[ 3 ] = +// [-0.0038066683095202003, -0.009526885008129744, 0.038838029990736031, -0.10492491909883139, 0.34636748878728713, 0.87736722339555218, -0.21106948651963514, 0.10635256340684114, -0.056702002655491461, 0.026758827510895762, -0.0082428187572101876] + +//poly_filter[ 4 ] = +// [-0.0082545095695661427, -7.8442979524903853e-17, 0.021386683884785231, -0.072504418238962198, 0.25376546383636761, 0.94101409093054489, -0.20118115883049581, 0.10455712121450497, -0.058561260885315596, 0.029854760451337354, -0.011202548701554096] + +//poly_filter[ 5 ] = +// [-0.011906242787328066, 0.008784760620874894, 0.0043136753630191298, -0.03984021212753959, 0.16582754988015289, 0.99237777483437095, -0.18069212746120333, 0.097709581878410862, -0.057722904308102688, 0.031645038861781369, -0.013734083296364351] + +//poly_filter[ 6 ] = +// [-0.014633125291013658, 0.016472060654605696, -0.011661896419860861, -0.008287046730187651, 0.08440464362663419, 1.030086410667886, -0.14915892799523031, 0.085699289017275276, -0.054016648119989123, 0.031930786250895349, -0.015657121608968226] + +//poly_filter[ 7 ] = +// [-0.016362250481865851, 0.022782281431648729, -0.025918813807834871, 0.020952344718333821, 0.011083035327064632, 1.053126546814495, -0.10646830143563842, 0.068636022936419336, -0.047397002279798629, 0.030576177554778709, -0.016813399068332405] + +//poly_filter[ 8 ] = +// [-0.017076787138575533, 0.027519682858549145, -0.037954085517163318, 0.046861549214532013, -0.052856519112105753, 1.0608764424006163, -0.052856519112105753, 0.046861549214532013, -0.037954085517163318, 0.027519682858549145, -0.017076787138575533] + +//poly_filter[ 9 ] = +// [-0.016813399068332405, 0.030576177554778709, -0.047397002279798629, 0.068636022936419336, -0.10646830143563842, 1.053126546814495, 0.011083035327064632, 0.020952344718333821, -0.025918813807834871, 0.022782281431648729, -0.016362250481865851] + +//poly_filter[ 10 ] = +// [-0.015657121608968226, 0.031930786250895349, -0.054016648119989123, 0.085699289017275276, -0.14915892799523031, 1.030086410667886, 0.08440464362663419, -0.008287046730187651, -0.011661896419860861, 0.016472060654605696, -0.014633125291013658] + +//poly_filter[ 11 ] = +// [-0.013734083296364351, 0.031645038861781369, -0.057722904308102688, 0.097709581878410862, -0.18069212746120333, 0.99237777483437095, 0.16582754988015289, -0.03984021212753959, 0.0043136753630191298, 0.008784760620874894, -0.011906242787328066] + +//poly_filter[ 12 ] = +// [-0.011202548701554096, 0.029854760451337354, -0.058561260885315596, 0.10455712121450497, -0.20118115883049581, 0.94101409093054489, 0.25376546383636761, -0.072504418238962198, 0.021386683884785231, -7.8442979524903853e-17, -0.0082545095695661427] + +//poly_filter[ 13 ] = +// [-0.0082428187572101876, 0.026758827510895762, -0.056702002655491461, 0.10635256340684114, -0.21106948651963514, 0.87736722339555218, 0.34636748878728713, -0.10492491909883139, 0.038838029990736031, -0.009526885008129744, -0.0038066683095202003] + +//poly_filter[ 14 ] = +// [-0.0050465560383613026, 0.022605592034878701, -0.052424552723671157, 0.1034075077591418, -0.21110075354176358, 0.80312255069339678, 0.4415692458117017, -0.13563705037865761, 0.055876818067479912, -0.01937724759416996, 0.0012559063894013399] + +//poly_filter[ 15 ] = +// [-0.00180610413580281, 0.017677745052985291, -0.046097928986694008, 0.096208216988318704, -0.2022794687055513, 0.72022410284524896, 0.53715256029912584, -0.16311478744344357, 0.071671349627165801, -0.029085429385636123, 0.0067053771043863149] + +// total_ntaps= 176 +// ntaps_per_filter= 11 +// nfilters= 16 +// filter resolution= 16 bits +// +//data_size= 5 phase_size= 4 +//abs_max= 1.5212482296 abs_max_16bit= 32767 signed_max_16bit= 32767 signed_min_16bit= -31514 +//nmemories= 3 +//incr_list = [15] +//bw= 16 data_size= 5 abs_max= 20515 len= 16 +module rrc_coeff_ram_generated1_0 (input clock, input strobe, input [3:0] phase, input [4:0] in_data, output [15:0] out_data,output [17:0] ext_out_data); + +reg reg_quadrant; +wire quadrant=in_data[4]; +wire [7:0] rd_addr={phase,quadrant?~in_data[3:0]:in_data[3:0]}; +reg [15:0] rd_data; + + always @(posedge clock) + if (strobe) + begin + reg_quadrant <= #1 quadrant; + case (rd_addr) + 8'd0 : rd_data <= #1 -16'd10866; + 8'd1 : rd_data <= #1 -16'd10338; + 8'd2 : rd_data <= #1 -16'd12510; + 8'd3 : rd_data <= #1 -16'd11981; + 8'd4 : rd_data <= #1 -16'd7188; + 8'd5 : rd_data <= #1 -16'd6659; + 8'd6 : rd_data <= #1 -16'd8832; + 8'd7 : rd_data <= #1 -16'd8303; + 8'd8 : rd_data <= #1 -16'd18872; + 8'd9 : rd_data <= #1 -16'd18343; + 8'd10 : rd_data <= #1 -16'd20515; + 8'd11 : rd_data <= #1 -16'd19987; + 8'd12 : rd_data <= #1 -16'd15193; + 8'd13 : rd_data <= #1 -16'd14664; + 8'd14 : rd_data <= #1 -16'd16837; + 8'd15 : rd_data <= #1 -16'd16308; + 8'd16 : rd_data <= #1 -16'd9118; + 8'd17 : rd_data <= #1 -16'd8829; + 8'd18 : rd_data <= #1 -16'd10371; + 8'd19 : rd_data <= #1 -16'd10082; + 8'd20 : rd_data <= #1 -16'd6031; + 8'd21 : rd_data <= #1 -16'd5742; + 8'd22 : rd_data <= #1 -16'd7284; + 8'd23 : rd_data <= #1 -16'd6995; + 8'd24 : rd_data <= #1 -16'd16145; + 8'd25 : rd_data <= #1 -16'd15856; + 8'd26 : rd_data <= #1 -16'd17398; + 8'd27 : rd_data <= #1 -16'd17109; + 8'd28 : rd_data <= #1 -16'd13058; + 8'd29 : rd_data <= #1 -16'd12769; + 8'd30 : rd_data <= #1 -16'd14311; + 8'd31 : rd_data <= #1 -16'd14022; + 8'd32 : rd_data <= #1 -16'd7403; + 8'd33 : rd_data <= #1 -16'd7349; + 8'd34 : rd_data <= #1 -16'd8238; + 8'd35 : rd_data <= #1 -16'd8184; + 8'd36 : rd_data <= #1 -16'd4996; + 8'd37 : rd_data <= #1 -16'd4942; + 8'd38 : rd_data <= #1 -16'd5831; + 8'd39 : rd_data <= #1 -16'd5776; + 8'd40 : rd_data <= #1 -16'd13246; + 8'd41 : rd_data <= #1 -16'd13192; + 8'd42 : rd_data <= #1 -16'd14081; + 8'd43 : rd_data <= #1 -16'd14027; + 8'd44 : rd_data <= #1 -16'd10839; + 8'd45 : rd_data <= #1 -16'd10785; + 8'd46 : rd_data <= #1 -16'd11674; + 8'd47 : rd_data <= #1 -16'd11620; + 8'd48 : rd_data <= #1 -16'd5750; + 8'd49 : rd_data <= #1 -16'd5914; + 8'd50 : rd_data <= #1 -16'd6160; + 8'd51 : rd_data <= #1 -16'd6324; + 8'd52 : rd_data <= #1 -16'd4077; + 8'd53 : rd_data <= #1 -16'd4241; + 8'd54 : rd_data <= #1 -16'd4487; + 8'd55 : rd_data <= #1 -16'd4651; + 8'd56 : rd_data <= #1 -16'd10270; + 8'd57 : rd_data <= #1 -16'd10434; + 8'd58 : rd_data <= #1 -16'd10680; + 8'd59 : rd_data <= #1 -16'd10844; + 8'd60 : rd_data <= #1 -16'd8597; + 8'd61 : rd_data <= #1 -16'd8761; + 8'd62 : rd_data <= #1 -16'd9007; + 8'd63 : rd_data <= #1 -16'd9171; + 8'd64 : rd_data <= #1 -16'd4187; + 8'd65 : rd_data <= #1 -16'd4543; + 8'd66 : rd_data <= #1 -16'd4187; + 8'd67 : rd_data <= #1 -16'd4543; + 8'd68 : rd_data <= #1 -16'd3266; + 8'd69 : rd_data <= #1 -16'd3621; + 8'd70 : rd_data <= #1 -16'd3266; + 8'd71 : rd_data <= #1 -16'd3621; + 8'd72 : rd_data <= #1 -16'd7311; + 8'd73 : rd_data <= #1 -16'd7666; + 8'd74 : rd_data <= #1 -16'd7311; + 8'd75 : rd_data <= #1 -16'd7666; + 8'd76 : rd_data <= #1 -16'd6389; + 8'd77 : rd_data <= #1 -16'd6745; + 8'd78 : rd_data <= #1 -16'd6389; + 8'd79 : rd_data <= #1 -16'd6745; + 8'd80 : rd_data <= #1 -16'd2739; + 8'd81 : rd_data <= #1 -16'd3252; + 8'd82 : rd_data <= #1 -16'd2361; + 8'd83 : rd_data <= #1 -16'd2874; + 8'd84 : rd_data <= #1 -16'd2554; + 8'd85 : rd_data <= #1 -16'd3066; + 8'd86 : rd_data <= #1 -16'd2175; + 8'd87 : rd_data <= #1 -16'd2688; + 8'd88 : rd_data <= #1 -16'd4456; + 8'd89 : rd_data <= #1 -16'd4969; + 8'd90 : rd_data <= #1 -16'd4077; + 8'd91 : rd_data <= #1 -16'd4590; + 8'd92 : rd_data <= #1 -16'd4270; + 8'd93 : rd_data <= #1 -16'd4783; + 8'd94 : rd_data <= #1 -16'd3891; + 8'd95 : rd_data <= #1 -16'd4404; + 8'd96 : rd_data <= #1 -16'd1428; + 8'd97 : rd_data <= #1 -16'd2058; + 8'd98 : rd_data <= #1 -16'd718; + 8'd99 : rd_data <= #1 -16'd1349; + 8'd100 : rd_data <= #1 -16'd1930; + 8'd101 : rd_data <= #1 -16'd2561; + 8'd102 : rd_data <= #1 -16'd1221; + 8'd103 : rd_data <= #1 -16'd1851; + 8'd104 : rd_data <= #1 -16'd1785; + 8'd105 : rd_data <= #1 -16'd2415; + 8'd106 : rd_data <= #1 -16'd1075; + 8'd107 : rd_data <= #1 -16'd1706; + 8'd108 : rd_data <= #1 -16'd2287; + 8'd109 : rd_data <= #1 -16'd2918; + 8'd110 : rd_data <= #1 -16'd1578; + 8'd111 : rd_data <= #1 -16'd2208; + 8'd112 : rd_data <= #1 -16'd270; + 8'd113 : rd_data <= #1 -16'd975; + 8'd114 : rd_data <= #1 16'd711; + 8'd115 : rd_data <= #1 16'd7; + 8'd116 : rd_data <= #1 -16'd1387; + 8'd117 : rd_data <= #1 -16'd2091; + 8'd118 : rd_data <= #1 -16'd405; + 8'd119 : rd_data <= #1 -16'd1110; + 8'd120 : rd_data <= #1 16'd633; + 8'd121 : rd_data <= #1 -16'd72; + 8'd122 : rd_data <= #1 16'd1614; + 8'd123 : rd_data <= #1 16'd909; + 8'd124 : rd_data <= #1 -16'd484; + 8'd125 : rd_data <= #1 -16'd1189; + 8'd126 : rd_data <= #1 16'd497; + 8'd127 : rd_data <= #1 -16'd207; + 8'd128 : rd_data <= #1 16'd722; + 8'd129 : rd_data <= #1 -16'd14; + 8'd130 : rd_data <= #1 16'd1907; + 8'd131 : rd_data <= #1 16'd1172; + 8'd132 : rd_data <= #1 -16'd913; + 8'd133 : rd_data <= #1 -16'd1649; + 8'd134 : rd_data <= #1 16'd272; + 8'd135 : rd_data <= #1 -16'd463; + 8'd136 : rd_data <= #1 16'd2740; + 8'd137 : rd_data <= #1 16'd2005; + 8'd138 : rd_data <= #1 16'd3926; + 8'd139 : rd_data <= #1 16'd3190; + 8'd140 : rd_data <= #1 16'd1105; + 8'd141 : rd_data <= #1 16'd370; + 8'd142 : rd_data <= #1 16'd2291; + 8'd143 : rd_data <= #1 16'd1555; + 8'd144 : rd_data <= #1 16'd1539; + 8'd145 : rd_data <= #1 16'd815; + 8'd146 : rd_data <= #1 16'd2857; + 8'd147 : rd_data <= #1 16'd2132; + 8'd148 : rd_data <= #1 -16'd502; + 8'd149 : rd_data <= #1 -16'd1227; + 8'd150 : rd_data <= #1 16'd815; + 8'd151 : rd_data <= #1 16'd90; + 8'd152 : rd_data <= #1 16'd4496; + 8'd153 : rd_data <= #1 16'd3772; + 8'd154 : rd_data <= #1 16'd5813; + 8'd155 : rd_data <= #1 16'd5089; + 8'd156 : rd_data <= #1 16'd2454; + 8'd157 : rd_data <= #1 16'd1730; + 8'd158 : rd_data <= #1 16'd3772; + 8'd159 : rd_data <= #1 16'd3047; + 8'd160 : rd_data <= #1 16'd2180; + 8'd161 : rd_data <= #1 16'd1505; + 8'd162 : rd_data <= #1 16'd3555; + 8'd163 : rd_data <= #1 16'd2881; + 8'd164 : rd_data <= #1 -16'd147; + 8'd165 : rd_data <= #1 -16'd822; + 8'd166 : rd_data <= #1 16'd1228; + 8'd167 : rd_data <= #1 16'd554; + 8'd168 : rd_data <= #1 16'd5872; + 8'd169 : rd_data <= #1 16'd5197; + 8'd170 : rd_data <= #1 16'd7247; + 8'd171 : rd_data <= #1 16'd6573; + 8'd172 : rd_data <= #1 16'd3545; + 8'd173 : rd_data <= #1 16'd2870; + 8'd174 : rd_data <= #1 16'd4920; + 8'd175 : rd_data <= #1 16'd4246; + 8'd176 : rd_data <= #1 16'd2645; + 8'd177 : rd_data <= #1 16'd2053; + 8'd178 : rd_data <= #1 16'd4008; + 8'd179 : rd_data <= #1 16'd3417; + 8'd180 : rd_data <= #1 16'd158; + 8'd181 : rd_data <= #1 -16'd433; + 8'd182 : rd_data <= #1 16'd1522; + 8'd183 : rd_data <= #1 16'd930; + 8'd184 : rd_data <= #1 16'd6854; + 8'd185 : rd_data <= #1 16'd6263; + 8'd186 : rd_data <= #1 16'd8217; + 8'd187 : rd_data <= #1 16'd7626; + 8'd188 : rd_data <= #1 16'd4368; + 8'd189 : rd_data <= #1 16'd3776; + 8'd190 : rd_data <= #1 16'd5731; + 8'd191 : rd_data <= #1 16'd5139; + 8'd192 : rd_data <= #1 16'd2941; + 8'd193 : rd_data <= #1 16'd2458; + 8'd194 : rd_data <= #1 16'd4227; + 8'd195 : rd_data <= #1 16'd3744; + 8'd196 : rd_data <= #1 16'd418; + 8'd197 : rd_data <= #1 -16'd65; + 8'd198 : rd_data <= #1 16'd1704; + 8'd199 : rd_data <= #1 16'd1222; + 8'd200 : rd_data <= #1 16'd7445; + 8'd201 : rd_data <= #1 16'd6962; + 8'd202 : rd_data <= #1 16'd8731; + 8'd203 : rd_data <= #1 16'd8249; + 8'd204 : rd_data <= #1 16'd4922; + 8'd205 : rd_data <= #1 16'd4440; + 8'd206 : rd_data <= #1 16'd6208; + 8'd207 : rd_data <= #1 16'd5726; + 8'd208 : rd_data <= #1 16'd3078; + 8'd209 : rd_data <= #1 16'd2723; + 8'd210 : rd_data <= #1 16'd4231; + 8'd211 : rd_data <= #1 16'd3876; + 8'd212 : rd_data <= #1 16'd635; + 8'd213 : rd_data <= #1 16'd280; + 8'd214 : rd_data <= #1 16'd1788; + 8'd215 : rd_data <= #1 16'd1433; + 8'd216 : rd_data <= #1 16'd7660; + 8'd217 : rd_data <= #1 16'd7305; + 8'd218 : rd_data <= #1 16'd8812; + 8'd219 : rd_data <= #1 16'd8457; + 8'd220 : rd_data <= #1 16'd5217; + 8'd221 : rd_data <= #1 16'd4862; + 8'd222 : rd_data <= #1 16'd6370; + 8'd223 : rd_data <= #1 16'd6015; + 8'd224 : rd_data <= #1 16'd3071; + 8'd225 : rd_data <= #1 16'd2853; + 8'd226 : rd_data <= #1 16'd4044; + 8'd227 : rd_data <= #1 16'd3827; + 8'd228 : rd_data <= #1 16'd812; + 8'd229 : rd_data <= #1 16'd595; + 8'd230 : rd_data <= #1 16'd1786; + 8'd231 : rd_data <= #1 16'd1569; + 8'd232 : rd_data <= #1 16'd7525; + 8'd233 : rd_data <= #1 16'd7308; + 8'd234 : rd_data <= #1 16'd8499; + 8'd235 : rd_data <= #1 16'd8282; + 8'd236 : rd_data <= #1 16'd5267; + 8'd237 : rd_data <= #1 16'd5050; + 8'd238 : rd_data <= #1 16'd6241; + 8'd239 : rd_data <= #1 16'd6023; + 8'd240 : rd_data <= #1 16'd2936; + 8'd241 : rd_data <= #1 16'd2858; + 8'd242 : rd_data <= #1 16'd3697; + 8'd243 : rd_data <= #1 16'd3620; + 8'd244 : rd_data <= #1 16'd950; + 8'd245 : rd_data <= #1 16'd872; + 8'd246 : rd_data <= #1 16'd1711; + 8'd247 : rd_data <= #1 16'd1634; + 8'd248 : rd_data <= #1 16'd7080; + 8'd249 : rd_data <= #1 16'd7003; + 8'd250 : rd_data <= #1 16'd7842; + 8'd251 : rd_data <= #1 16'd7764; + 8'd252 : rd_data <= #1 16'd5094; + 8'd253 : rd_data <= #1 16'd5017; + 8'd254 : rd_data <= #1 16'd5856; + 8'd255 : rd_data <= #1 16'd5778; + endcase // case(rd_addr) + end //if (strobe) + assign out_data[15:0]=reg_quadrant?-rd_data:rd_data; + sign_extend #(16,18) + ext_output (.in(out_data),.out(ext_out_data)); + +endmodule // rrc_coeff_ram_generated_0 + +//bw= 16 data_size= 5 abs_max= 32767 len= 16 +module rrc_coeff_ram_generated1_1 (input clock, input strobe, input [3:0] phase, input [4:0] in_data, output [15:0] out_data,output [17:0] ext_out_data); + +reg reg_quadrant; +wire quadrant=in_data[4]; +wire [7:0] rd_addr={phase,quadrant?~in_data[3:0]:in_data[3:0]}; +reg [15:0] rd_data; + + always @(posedge clock) + if (strobe) + begin + reg_quadrant <= #1 quadrant; + case (rd_addr) + 8'd0 : rd_data <= #1 -16'd10866; + 8'd1 : rd_data <= #1 16'd16308; + 8'd2 : rd_data <= #1 -16'd18872; + 8'd3 : rd_data <= #1 16'd8303; + 8'd4 : rd_data <= #1 -16'd7188; + 8'd5 : rd_data <= #1 16'd19987; + 8'd6 : rd_data <= #1 -16'd15193; + 8'd7 : rd_data <= #1 16'd11981; + 8'd8 : rd_data <= #1 -16'd12510; + 8'd9 : rd_data <= #1 16'd14664; + 8'd10 : rd_data <= #1 -16'd20515; + 8'd11 : rd_data <= #1 16'd6659; + 8'd12 : rd_data <= #1 -16'd8832; + 8'd13 : rd_data <= #1 16'd18343; + 8'd14 : rd_data <= #1 -16'd16837; + 8'd15 : rd_data <= #1 16'd10338; + 8'd16 : rd_data <= #1 -16'd12616; + 8'd17 : rd_data <= #1 16'd18410; + 8'd18 : rd_data <= #1 -16'd21330; + 8'd19 : rd_data <= #1 16'd9696; + 8'd20 : rd_data <= #1 -16'd8472; + 8'd21 : rd_data <= #1 16'd22555; + 8'd22 : rd_data <= #1 -16'd17186; + 8'd23 : rd_data <= #1 16'd13841; + 8'd24 : rd_data <= #1 -16'd14602; + 8'd25 : rd_data <= #1 16'd16424; + 8'd26 : rd_data <= #1 -16'd23316; + 8'd27 : rd_data <= #1 16'd7710; + 8'd28 : rd_data <= #1 -16'd10458; + 8'd29 : rd_data <= #1 16'd20569; + 8'd30 : rd_data <= #1 -16'd19172; + 8'd31 : rd_data <= #1 16'd11855; + 8'd32 : rd_data <= #1 -16'd14337; + 8'd33 : rd_data <= #1 16'd20261; + 8'd34 : rd_data <= #1 -16'd23431; + 8'd35 : rd_data <= #1 16'd11167; + 8'd36 : rd_data <= #1 -16'd9882; + 8'd37 : rd_data <= #1 16'd24716; + 8'd38 : rd_data <= #1 -16'd18976; + 8'd39 : rd_data <= #1 16'd15622; + 8'd40 : rd_data <= #1 -16'd16595; + 8'd41 : rd_data <= #1 16'd18002; + 8'd42 : rd_data <= #1 -16'd25689; + 8'd43 : rd_data <= #1 16'd8908; + 8'd44 : rd_data <= #1 -16'd12141; + 8'd45 : rd_data <= #1 16'd22457; + 8'd46 : rd_data <= #1 -16'd21235; + 8'd47 : rd_data <= #1 16'd13363; + 8'd48 : rd_data <= #1 -16'd15998; + 8'd49 : rd_data <= #1 16'd21799; + 8'd50 : rd_data <= #1 -16'd25090; + 8'd51 : rd_data <= #1 16'd12706; + 8'd52 : rd_data <= #1 -16'd11416; + 8'd53 : rd_data <= #1 16'd26380; + 8'd54 : rd_data <= #1 -16'd20509; + 8'd55 : rd_data <= #1 16'd17288; + 8'd56 : rd_data <= #1 -16'd18440; + 8'd57 : rd_data <= #1 16'd19356; + 8'd58 : rd_data <= #1 -16'd27533; + 8'd59 : rd_data <= #1 16'd10263; + 8'd60 : rd_data <= #1 -16'd13859; + 8'd61 : rd_data <= #1 16'd23938; + 8'd62 : rd_data <= #1 -16'd22951; + 8'd63 : rd_data <= #1 16'd14845; + 8'd64 : rd_data <= #1 -16'd17569; + 8'd65 : rd_data <= #1 16'd22969; + 8'd66 : rd_data <= #1 -16'd26236; + 8'd67 : rd_data <= #1 16'd14302; + 8'd68 : rd_data <= #1 -16'd13065; + 8'd69 : rd_data <= #1 16'd27473; + 8'd70 : rd_data <= #1 -16'd21732; + 8'd71 : rd_data <= #1 16'd18806; + 8'd72 : rd_data <= #1 -16'd20092; + 8'd73 : rd_data <= #1 16'd20446; + 8'd74 : rd_data <= #1 -16'd28759; + 8'd75 : rd_data <= #1 16'd11779; + 8'd76 : rd_data <= #1 -16'd15588; + 8'd77 : rd_data <= #1 16'd24950; + 8'd78 : rd_data <= #1 -16'd24255; + 8'd79 : rd_data <= #1 16'd16283; + 8'd80 : rd_data <= #1 -16'd19026; + 8'd81 : rd_data <= #1 16'd23724; + 8'd82 : rd_data <= #1 -16'd26810; + 8'd83 : rd_data <= #1 16'd15940; + 8'd84 : rd_data <= #1 -16'd14817; + 8'd85 : rd_data <= #1 16'd27934; + 8'd86 : rd_data <= #1 -16'd22601; + 8'd87 : rd_data <= #1 16'd20150; + 8'd88 : rd_data <= #1 -16'd21513; + 8'd89 : rd_data <= #1 16'd21238; + 8'd90 : rd_data <= #1 -16'd29297; + 8'd91 : rd_data <= #1 16'd13454; + 8'd92 : rd_data <= #1 -16'd17304; + 8'd93 : rd_data <= #1 16'd25447; + 8'd94 : rd_data <= #1 -16'd25088; + 8'd95 : rd_data <= #1 16'd17663; + 8'd96 : rd_data <= #1 -16'd20345; + 8'd97 : rd_data <= #1 16'd24030; + 8'd98 : rd_data <= #1 -16'd26771; + 8'd99 : rd_data <= #1 16'd17605; + 8'd100 : rd_data <= #1 -16'd16653; + 8'd101 : rd_data <= #1 16'd27722; + 8'd102 : rd_data <= #1 -16'd23079; + 8'd103 : rd_data <= #1 16'd21296; + 8'd104 : rd_data <= #1 -16'd22672; + 8'd105 : rd_data <= #1 16'd21703; + 8'd106 : rd_data <= #1 -16'd29098; + 8'd107 : rd_data <= #1 16'd15278; + 8'd108 : rd_data <= #1 -16'd18980; + 8'd109 : rd_data <= #1 16'd25395; + 8'd110 : rd_data <= #1 -16'd25406; + 8'd111 : rd_data <= #1 16'd18969; + 8'd112 : rd_data <= #1 -16'd21507; + 8'd113 : rd_data <= #1 16'd23861; + 8'd114 : rd_data <= #1 -16'd26093; + 8'd115 : rd_data <= #1 16'd19275; + 8'd116 : rd_data <= #1 -16'd18550; + 8'd117 : rd_data <= #1 16'd26818; + 8'd118 : rd_data <= #1 -16'd23136; + 8'd119 : rd_data <= #1 16'd22231; + 8'd120 : rd_data <= #1 -16'd23548; + 8'd121 : rd_data <= #1 16'd21819; + 8'd122 : rd_data <= #1 -16'd28135; + 8'd123 : rd_data <= #1 16'd17233; + 8'd124 : rd_data <= #1 -16'd20592; + 8'd125 : rd_data <= #1 16'd24776; + 8'd126 : rd_data <= #1 -16'd25178; + 8'd127 : rd_data <= #1 16'd20189; + 8'd128 : rd_data <= #1 -16'd22497; + 8'd129 : rd_data <= #1 16'd23205; + 8'd130 : rd_data <= #1 -16'd24774; + 8'd131 : rd_data <= #1 16'd20928; + 8'd132 : rd_data <= #1 -16'd20478; + 8'd133 : rd_data <= #1 16'd25223; + 8'd134 : rd_data <= #1 -16'd22755; + 8'd135 : rd_data <= #1 16'd22946; + 8'd136 : rd_data <= #1 -16'd24132; + 8'd137 : rd_data <= #1 16'd21570; + 8'd138 : rd_data <= #1 -16'd26409; + 8'd139 : rd_data <= #1 16'd19293; + 8'd140 : rd_data <= #1 -16'd22113; + 8'd141 : rd_data <= #1 16'd23588; + 8'd142 : rd_data <= #1 -16'd24390; + 8'd143 : rd_data <= #1 16'd21311; + 8'd144 : rd_data <= #1 -16'd23306; + 8'd145 : rd_data <= #1 16'd22061; + 8'd146 : rd_data <= #1 -16'd22829; + 8'd147 : rd_data <= #1 16'd22539; + 8'd148 : rd_data <= #1 -16'd22404; + 8'd149 : rd_data <= #1 16'd22964; + 8'd150 : rd_data <= #1 -16'd21926; + 8'd151 : rd_data <= #1 16'd23441; + 8'd152 : rd_data <= #1 -16'd24423; + 8'd153 : rd_data <= #1 16'd20945; + 8'd154 : rd_data <= #1 -16'd23945; + 8'd155 : rd_data <= #1 16'd21422; + 8'd156 : rd_data <= #1 -16'd23520; + 8'd157 : rd_data <= #1 16'd21847; + 8'd158 : rd_data <= #1 -16'd23043; + 8'd159 : rd_data <= #1 16'd22325; + 8'd160 : rd_data <= #1 -16'd23931; + 8'd161 : rd_data <= #1 16'd20444; + 8'd162 : rd_data <= #1 -16'd20295; + 8'd163 : rd_data <= #1 16'd24081; + 8'd164 : rd_data <= #1 -16'd24288; + 8'd165 : rd_data <= #1 16'd20087; + 8'd166 : rd_data <= #1 -16'd20652; + 8'd167 : rd_data <= #1 16'd23724; + 8'd168 : rd_data <= #1 -16'd24433; + 8'd169 : rd_data <= #1 16'd19942; + 8'd170 : rd_data <= #1 -16'd20797; + 8'd171 : rd_data <= #1 16'd23578; + 8'd172 : rd_data <= #1 -16'd24790; + 8'd173 : rd_data <= #1 16'd19585; + 8'd174 : rd_data <= #1 -16'd21154; + 8'd175 : rd_data <= #1 16'd23221; + 8'd176 : rd_data <= #1 -16'd24371; + 8'd177 : rd_data <= #1 16'd18380; + 8'd178 : rd_data <= #1 -16'd17228; + 8'd179 : rd_data <= #1 16'd25523; + 8'd180 : rd_data <= #1 -16'd26087; + 8'd181 : rd_data <= #1 16'd16663; + 8'd182 : rd_data <= #1 -16'd18944; + 8'd183 : rd_data <= #1 16'd23807; + 8'd184 : rd_data <= #1 -16'd24185; + 8'd185 : rd_data <= #1 16'd18565; + 8'd186 : rd_data <= #1 -16'd17042; + 8'd187 : rd_data <= #1 16'd25709; + 8'd188 : rd_data <= #1 -16'd25902; + 8'd189 : rd_data <= #1 16'd16849; + 8'd190 : rd_data <= #1 -16'd18758; + 8'd191 : rd_data <= #1 16'd23993; + 8'd192 : rd_data <= #1 -16'd24634; + 8'd193 : rd_data <= #1 16'd15904; + 8'd194 : rd_data <= #1 -16'd13702; + 8'd195 : rd_data <= #1 16'd26836; + 8'd196 : rd_data <= #1 -16'd27757; + 8'd197 : rd_data <= #1 16'd12781; + 8'd198 : rd_data <= #1 -16'd16825; + 8'd199 : rd_data <= #1 16'd23713; + 8'd200 : rd_data <= #1 -16'd23713; + 8'd201 : rd_data <= #1 16'd16825; + 8'd202 : rd_data <= #1 -16'd12781; + 8'd203 : rd_data <= #1 16'd27757; + 8'd204 : rd_data <= #1 -16'd26836; + 8'd205 : rd_data <= #1 16'd13702; + 8'd206 : rd_data <= #1 -16'd15904; + 8'd207 : rd_data <= #1 16'd24634; + 8'd208 : rd_data <= #1 -16'd24730; + 8'd209 : rd_data <= #1 16'd13066; + 8'd210 : rd_data <= #1 -16'd9809; + 8'd211 : rd_data <= #1 16'd27987; + 8'd212 : rd_data <= #1 -16'd29250; + 8'd213 : rd_data <= #1 16'd8546; + 8'd214 : rd_data <= #1 -16'd14329; + 8'd215 : rd_data <= #1 16'd23467; + 8'd216 : rd_data <= #1 -16'd23057; + 8'd217 : rd_data <= #1 16'd14739; + 8'd218 : rd_data <= #1 -16'd8136; + 8'd219 : rd_data <= #1 16'd29660; + 8'd220 : rd_data <= #1 -16'd27577; + 8'd221 : rd_data <= #1 16'd10219; + 8'd222 : rd_data <= #1 -16'd12656; + 8'd223 : rd_data <= #1 16'd25140; + 8'd224 : rd_data <= #1 -16'd24675; + 8'd225 : rd_data <= #1 16'd9923; + 8'd226 : rd_data <= #1 -16'd5652; + 8'd227 : rd_data <= #1 16'd28945; + 8'd228 : rd_data <= #1 -16'd30518; + 8'd229 : rd_data <= #1 16'd4080; + 8'd230 : rd_data <= #1 -16'd11495; + 8'd231 : rd_data <= #1 16'd23102; + 8'd232 : rd_data <= #1 -16'd22268; + 8'd233 : rd_data <= #1 16'd12330; + 8'd234 : rd_data <= #1 -16'd3245; + 8'd235 : rd_data <= #1 16'd31353; + 8'd236 : rd_data <= #1 -16'd28111; + 8'd237 : rd_data <= #1 16'd6487; + 8'd238 : rd_data <= #1 -16'd9088; + 8'd239 : rd_data <= #1 16'd25509; + 8'd240 : rd_data <= #1 -16'd24487; + 8'd241 : rd_data <= #1 16'd6539; + 8'd242 : rd_data <= #1 -16'd1347; + 8'd243 : rd_data <= #1 16'd29679; + 8'd244 : rd_data <= #1 -16'd31514; + 8'd245 : rd_data <= #1 -16'd487; + 8'd246 : rd_data <= #1 -16'd8374; + 8'd247 : rd_data <= #1 16'd22653; + 8'd248 : rd_data <= #1 -16'd21400; + 8'd249 : rd_data <= #1 16'd9627; + 8'd250 : rd_data <= #1 16'd1740; + 8'd251 : rd_data <= #1 16'd32767; + 8'd252 : rd_data <= #1 -16'd28426; + 8'd253 : rd_data <= #1 16'd2600; + 8'd254 : rd_data <= #1 -16'd5286; + 8'd255 : rd_data <= #1 16'd25740; + endcase // case(rd_addr) + end //if (strobe) + assign out_data[15:0]=reg_quadrant?-rd_data:rd_data; + sign_extend #(16,18) + ext_output (.in(out_data),.out(ext_out_data)); + +endmodule // rrc_coeff_ram_generated_1 + +//bw= 10 data_size= 1 abs_max= 368 len= 1 +module rrc_coeff_ram_generated1_2 (input clock, input strobe, input [3:0] phase, input [0:0] in_data, output [9:0] out_data,output [17:0] ext_out_data); + +reg reg_quadrant; +wire quadrant=in_data[0]; +wire [3:0] rd_addr=phase; +reg [9:0] rd_data; + + always @(posedge clock) + if (strobe) + begin + reg_quadrant <= #1 quadrant; + case (rd_addr) + 4'd0 : rd_data <= #1 -10'd28; + 4'd1 : rd_data <= #1 10'd39; + 4'd2 : rd_data <= #1 10'd109; + 4'd3 : rd_data <= #1 10'd178; + 4'd4 : rd_data <= #1 10'd241; + 4'd5 : rd_data <= #1 10'd296; + 4'd6 : rd_data <= #1 10'd337; + 4'd7 : rd_data <= #1 10'd362; + 4'd8 : rd_data <= #1 10'd368; + 4'd9 : rd_data <= #1 10'd352; + 4'd10 : rd_data <= #1 10'd315; + 4'd11 : rd_data <= #1 10'd256; + 4'd12 : rd_data <= #1 10'd178; + 4'd13 : rd_data <= #1 10'd82; + 4'd14 : rd_data <= #1 -10'd27; + 4'd15 : rd_data <= #1 -10'd144; + endcase // case(rd_addr) + end //if (strobe) + assign out_data[9:0]=reg_quadrant?-rd_data:rd_data; + sign_extend #(10,18) + ext_output (.in(out_data),.out(ext_out_data)); + +endmodule // rrc_coeff_ram_generated_2 + +//bw_memory [4, 4, 0] data_size 5 +module frac_interp_1 + + (input clock, input reset, input enable, + output reg strobe_in, input strobe_out, + input wire [4:0] tx_shift, + input wire [15:0] signal_in, + output reg [15:0] signal_out); + +reg [3:0] phase;//max 16 phases + +reg [3:0] in_count;//16 bits in every register + +reg [15:0] input_16; + +reg [15:0] shift_16_0; +wire get_bit= (phase==4'd15); + + always @(posedge clock) + if (reset) + begin + strobe_in <= #1 0;// Reset + in_count <=#1 0; + input_16 <= #1 0; + + shift_16_0 <= #1 0; + + end //if (reset) + else //if (reset) + begin + if(enable & strobe_out & get_bit & (in_count == 4'd15)) + strobe_in <=#1 1'd1;//Only works if output of previous stage is registered and only updates on this strobe_in + else // if(strobe_in) //input a new 16 bit word and shift all regs 16 bit to the right= to next register) + strobe_in <= #1 0;//notice the else is always executed, even if there is no strobe_out so strobe_in will only be high for 1 clock + + if (enable & strobe_out) + begin + if ( get_bit) + + begin //shift input 1 bit to the left + if(in_count == 4'd15) //(strobe_in) //if(in_count == 4'd0) + begin + //strobe_in <=#1 1'd1;//Only works if output of previous stage is registered and only updates on this strobe_in + input_16 <= #1 signal_in; + end //if(in_count == 4'd0) + else //if(in_count == 4'd0) + begin + input_16 <= #1 {1'd0,input_16[15:1]};//just shift right //MDVH 14feb2007 + //input_16 <= #1 {input_16[14:0],1'd0};//just shift left //MDVH 14feb2007 + end // if(in_count == 4'd0) else + //shift_16_0 <= #1 {shift_16_0[14:0],input_16[15]};//MDVH 14feb2007 + shift_16_0 <= #1 {input_16[0],shift_16_0[15:1]};//MDVH 14feb2007 + + + in_count <= #1 in_count+4'd1; + end //if ((phase==.... + end //if (enable & strobe_out) + end // if (reset) else + + always @(posedge clock) + if (reset) + phase <=#1 0; + else if (enable & strobe_out) + phase <=#1 phase + 4'd1;//phase will roll-over to zero and start again + + +wire [4:0] data_0; +wire [4:0] data_1; +wire [0:0] data_2; +assign data_2=shift_16_0[10:10]; +assign data_1=shift_16_0[9:5]; +assign data_0=shift_16_0[4:0]; +wire [17:0] sum_0; +wire [17:0] sum_1; +wire [17:0] sum_2; +wire [17:0] sum_3; +assign sum_3=0; +reg [17:0] sum_all; + +//wire [15:0] sum_all_16bit; + + rrc_coeff_ram_generated1_0 rrc_coeff_ram_0 ( .clock(clock),.strobe(strobe_out),.phase(phase),.in_data(data_0),.out_data(),.ext_out_data(sum_0) ); + rrc_coeff_ram_generated1_1 rrc_coeff_ram_1 ( .clock(clock),.strobe(strobe_out),.phase(phase),.in_data(data_1),.out_data(),.ext_out_data(sum_1) ); + rrc_coeff_ram_generated1_2 rrc_coeff_ram_2 ( .clock(clock),.strobe(strobe_out),.phase(phase),.in_data(data_2),.out_data(),.ext_out_data(sum_2) ); +//assign sum_all= sum_0 + sum_1 + sum_2; +reg [17:0] sum_01; +reg [17:0] sum_23; +reg [17:0] sum_0123; + + always @(posedge clock) + if (reset) + begin + + sum_01 <= #1 0; + sum_23 <= #1 0; + sum_0123 <= #1 0; + + sum_all <=#1 0; + signal_out <= #1 0; + end + else if (enable & strobe_out) + begin + + sum_01 <= #1 sum_0+sum_1; + sum_23 <= #1 sum_2+sum_3; + sum_0123 <= #1 sum_01+sum_23; + sum_all <= #1 sum_0123; + + case(tx_shift) + //5'd0 : signal_out <= #1 round_16(sum_all);//no gain reduce + 5'd0 : signal_out <= #1 { sum_all[16:1] + (sum_all[17] & ( sum_all[0] )) }; + 5'd1 : signal_out <= #1 { sum_all[17:2] + (sum_all[17] & (|sum_all[1:0])) }; + 5'd2 : signal_out <= #1 { {{(1){sum_all[17]}}, sum_all[17:3]} + (sum_all[17] & (|sum_all[2:0])) }; + 5'd3 : signal_out <= #1 { {{(2){sum_all[17]}}, sum_all[17:4]} + (sum_all[17] & (|sum_all[3:0])) }; + 5'd4 : signal_out <= #1 { {{(3){sum_all[17]}}, sum_all[17:5]} + (sum_all[17] & (|sum_all[4:0])) }; + 5'd5 : signal_out <= #1 { {{(4){sum_all[17]}}, sum_all[17:6]} + (sum_all[17] & (|sum_all[5:0])) }; + 5'd6 : signal_out <= #1 { {{(5){sum_all[17]}}, sum_all[17:7]} + (sum_all[17] & (|sum_all[6:0])) }; + 5'd7 : signal_out <= #1 { {{(6){sum_all[17]}}, sum_all[17:8]} + (sum_all[17] & (|sum_all[7:0])) }; + 5'd8 : signal_out <= #1 { {{(7){sum_all[17]}}, sum_all[17:9]} + (sum_all[17] & (|sum_all[8:0])) }; + 5'd9 : signal_out <= #1 { {{(8){sum_all[17]}}, sum_all[17:10]} + (sum_all[17] & (|sum_all[9:0])) }; + 5'd10 : signal_out <= #1 { {{(9){sum_all[17]}},sum_all[17:11]} + (sum_all[17] & (|sum_all[10:0]))}; + 5'd11 : signal_out <= #1 { {{(10){sum_all[17]}},sum_all[17:12]} + (sum_all[17] & (|sum_all[11:0]))}; + 5'd12 : signal_out <= #1 { {{(11){sum_all[17]}},sum_all[17:13]} + (sum_all[17] & (|sum_all[12:0]))}; + 5'd13 : signal_out <= #1 { {{(12){sum_all[17]}},sum_all[17:14]} + (sum_all[17] & (|sum_all[13:0]))}; + 5'd14 : signal_out <= #1 { {{(13){sum_all[17]}},sum_all[17:15]} + (sum_all[17] & (|sum_all[14:0]))}; + 5'd15 : signal_out <= #1 { {{(14){sum_all[17]}},sum_all[17:16]} + (sum_all[17] & (|sum_all[15:0]))}; + + -5'd1 : signal_out <= #1 {sum_all[15:0] }; + -5'd2 : signal_out <= #1 {sum_all[14:0] ,{(1){1'b0}}}; + -5'd3 : signal_out <= #1 {sum_all[13:0] ,{(2){1'b0}}}; + -5'd4 : signal_out <= #1 {sum_all[12:0] ,{(3){1'b0}}}; + -5'd5 : signal_out <= #1 {sum_all[11:0] ,{(4){1'b0}}}; + -5'd6 : signal_out <= #1 {sum_all[10:0] ,{(5){1'b0}}}; + -5'd7 : signal_out <= #1 {sum_all[9:0] ,{(6){1'b0}}}; + -5'd8 : signal_out <= #1 {sum_all[8:0] ,{(7){1'b0}}}; + -5'd9 : signal_out <= #1 {sum_all[7:0] ,{(8){1'b0}}}; + -5'd10 : signal_out <= #1 {sum_all[6:0] ,{(9){1'b0}}}; + -5'd11 : signal_out <= #1 {sum_all[5:0] ,{(10){1'b0}}}; + -5'd12 : signal_out <= #1 {sum_all[4:0] ,{(11){1'b0}}}; + -5'd13 : signal_out <= #1 {sum_all[3:0] ,{(12){1'b0}}}; + -5'd14 : signal_out <= #1 {sum_all[2:0] ,{(13){1'b0}}}; + -5'd15 : signal_out <= #1 {sum_all[1:0] ,{(14){1'b0}}}; + + default : signal_out <= #1 { sum_all[16:1] + (sum_all[17] & ( sum_all[0] )) }; + //signal_out <= #1 { sum_all[17:2] + (sum_all[17] & (|sum_all[1:0])) }; + endcase // case(shift) + + //sum_all_14bit <= #1 sum_0123[16:3] + (sum_0123[16] & |sum_0123[2:0]);//round to 14 bit (reduce gain by 2 bit = 12 dB) + + //signal_out <= #1 round_16(sum_all);//no gain reduce + //signal_out <= #1 {{(2){sum_all_14bit[13]}},sum_all_14bit};//sign_extend to 16 bit (gain reduced by 2 bit = 12 dB) + + end //else if (enable & strobe_out) + + +/*assign sum_all_16bit=round_16(sum_all); +//register the output to ease timing of the DDR DAC output + always @(posedge clock or posedge reset) + if (reset) + signal_out <= #1 0; // Reset + else + signal_out <= #1 sum_all_16bit; +*/ +//round to 16 bit +// function [15:0] round_16; +// input [16:0] in_val; +// round_16 = in_val[16:1] + (in_val[16] & |in_val[0]);//round_16 = in_val[16:1] + (in_val[16] & in_val[0]) +// endfunction // round_16 + + +endmodule //module frac_interp_1 Index: usrp/fpga/sdr_lib/frac_interp_0.v =================================================================== --- usrp/fpga/sdr_lib/frac_interp_0.v (revision 0) +++ usrp/fpga/sdr_lib/frac_interp_0.v (revision 0) @@ -0,0 +1,879 @@ +// -*- verilog -*- +// +// Polyphase interpolating Root-Raised-Cosine filter +// +// Copyright (C) 2007 Martin Dudok van Heel +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// +// Polyphase interpolating Root-Raised-Cosine filter +// Interpolation ratio can be fractional (float) +// +// This file was generated by ./generate_frac_interp_05nov2007.py at 2007-11-08 00:15:22.695709 +// Written by Martin Dudok van Heel, 2007 +// Olifantasia +// +// Contact: http://www.olifantasia.com/gnuradio/contact.gif or nldudok1_olifantasia_com +// http://www.olifantasia.com +// +// This file can be used to build a special purpose firmware for the USRP +// USRP = Universal Software Radio Peripheral +// This special purpose firmware in combination with the GnuRadio framework can be used to create a high speed QPSK transmitter +// Depending on the decimation and interpolation factors used, the symbolrate can be from 2 to 20 Msymbols/sec +// The corresponding QPSK bitrate is 4 to 40 Mbit/sec +// alpha= 0.35 +// interpolation = 16.0 decimation= 1.0 interp_ratio= 16.0 decim_ratio= 0.0625 +// symbol rate = 2.0 Msymbol/sec +// QPSK bitrate = 4.0 Mbit/sec +// +//fractional ntaps 176.0 +//ntaps_per_filter= 11 +//nfilters= 16 +// s f incr d_mu ii oo step +// 0.0 0.0 0 0.0 0 0 0 +// 0.0625 0.0 0 0.0625 0 1 1 +// 0.125 0.0 0 0.125 0 2 2 +// 0.1875 0.0 0 0.1875 0 3 3 +// 0.25 0.0 0 0.25 0 4 4 +// 0.3125 0.0 0 0.3125 0 5 5 +// 0.375 0.0 0 0.375 0 6 6 +// 0.4375 0.0 0 0.4375 0 7 7 +// 0.5 0.0 0 0.5 0 8 8 +// 0.5625 0.0 0 0.5625 0 9 9 +// 0.625 0.0 0 0.625 0 10 10 +// 0.6875 0.0 0 0.6875 0 11 11 +// 0.75 0.0 0 0.75 0 12 12 +// 0.8125 0.0 0 0.8125 0 13 13 +// 0.875 0.0 0 0.875 0 14 14 +// 0.9375 0.0 0 0.9375 0 15 15 +//poly_filter[ 0 ] = +// [-0.011587695450775884, 0.009540331775325591, 0.025529243999645228, -0.13471163423240112, 0.60573900392913038, 0.60573900392913038, -0.13471163423240112, 0.025529243999645228, 0.009540331775325591, -0.011587695450775884, 0.0027409495713674546] + +//poly_filter[ 1 ] = +// [-0.0099778106805516343, 0.012243898388679795, 0.01381187210553937, -0.10784673839600598, 0.5036516325587086, 0.70461324036848649, -0.15789857108157021, 0.037306542075417615, 0.0057724100313517913, -0.012484351992881374, 0.0047621700874819917] + +//poly_filter[ 2 ] = +// [-0.0077900979459937601, 0.013770041692387745, 0.0028393004067138075, -0.079043142889963613, 0.40121981446161492, 0.79740634077856587, -0.17563700569215573, 0.048374957455653546, 0.0011409471925254001, -0.012575432872464706, 0.0065948029259533299] + +//poly_filter[ 3 ] = +// [-0.0051918884379789634, 0.014094235134993529, -0.0068180138195810215, -0.049936985728082653, 0.30120806330766442, 0.88135824274746832, -0.1862032652736608, 0.057919959029894712, -0.0040722547133090715, -0.011820412465814426, 0.0081011166648467508] + +//poly_filter[ 4 ] = +// [-0.002369808994513568, 0.013275670848030585, -0.014725700012165777, -0.021998743447974509, 0.20617867436174767, 0.95392185609796487, -0.18800158643030346, 0.065125644071244701, -0.0095171104656519498, -0.010236276383968073, 0.0091588581512722211] + +//poly_filter[ 5 ] = +// [0.00048347260723167232, 0.011447479369610835, -0.020597793357802315, 0.0035176129499998993, 0.11840454095660065, 1.0128613066927243, -0.17964431069970466, 0.069223183473694869, -0.014793509202544011, -0.0078995715847417682, 0.0096704811556829768] + +//poly_filter[ 6 ] = +// [0.0031822326226663175, 0.008802914171020677, -0.024299705383391313, 0.02561204350538385, 0.039796304923507324, 1.0563390719129626, -0.16002739061571231, 0.069540957150195037, -0.019474353322261367, -0.004944470036472381, 0.0095711139086369253] + +//poly_filter[ 7 ] = +// [0.0055595783615640876, 0.0055786140616833589, -0.025842360059079271, 0.0435614578372319, -0.028153407707346888, 1.0829881487676363, -0.12839743104636323, 0.065553728158199417, -0.023132255200493404, -0.0015567455703022638, 0.0088346592297861831] + +//poly_filter[ 8 ] = +// [0.0074775197590773203, 0.0020361698472420751, -0.025368464034228311, 0.05692809049980125, -0.084406752442248281, 1.0919660406286562, -0.084406752442248281, 0.05692809049980125, -0.025368464034228311, 0.0020361698472420751, 0.0074775197590773203] + +//poly_filter[ 9 ] = +// [0.0088346592297861831, -0.0015567455703022638, -0.023132255200493404, 0.065553728158199417, -0.12839743104636323, 1.0829881487676363, -0.028153407707346888, 0.0435614578372319, -0.025842360059079271, 0.0055786140616833589, 0.0055595783615640876] + +//poly_filter[ 10 ] = +// [0.0095711139086369253, -0.004944470036472381, -0.019474353322261367, 0.069540957150195037, -0.16002739061571231, 1.0563390719129626, 0.039796304923507324, 0.02561204350538385, -0.024299705383391313, 0.008802914171020677, 0.0031822326226663175] + +//poly_filter[ 11 ] = +// [0.0096704811556829768, -0.0078995715847417682, -0.014793509202544011, 0.069223183473694869, -0.17964431069970466, 1.0128613066927243, 0.11840454095660065, 0.0035176129499998993, -0.020597793357802315, 0.011447479369610835, 0.00048347260723167232] + +//poly_filter[ 12 ] = +// [0.0091588581512722211, -0.010236276383968073, -0.0095171104656519498, 0.065125644071244701, -0.18800158643030346, 0.95392185609796487, 0.20617867436174767, -0.021998743447974509, -0.014725700012165777, 0.013275670848030585, -0.002369808994513568] + +//poly_filter[ 13 ] = +// [0.0081011166648467508, -0.011820412465814426, -0.0040722547133090715, 0.057919959029894712, -0.1862032652736608, 0.88135824274746832, 0.30120806330766442, -0.049936985728082653, -0.0068180138195810215, 0.014094235134993529, -0.0051918884379789634] + +//poly_filter[ 14 ] = +// [0.0065948029259533299, -0.012575432872464706, 0.0011409471925254001, 0.048374957455653546, -0.17563700569215573, 0.79740634077856587, 0.40121981446161492, -0.079043142889963613, 0.0028393004067138075, 0.013770041692387745, -0.0077900979459937601] + +//poly_filter[ 15 ] = +// [0.0047621700874819917, -0.012484351992881374, 0.0057724100313517913, 0.037306542075417615, -0.15789857108157021, 0.70461324036848649, 0.5036516325587086, -0.10784673839600598, 0.01381187210553937, 0.012243898388679795, -0.0099778106805516343] + +// total_ntaps= 176 +// ntaps_per_filter= 11 +// nfilters= 16 +// filter resolution= 16 bits +// +//data_size= 5 phase_size= 4 +//abs_max= 1.34216738182 abs_max_16bit= 32767 signed_max_16bit= 32169 signed_min_16bit= -32767 +//nmemories= 3 +//incr_list = [15] +//bw= 16 data_size= 5 abs_max= 19216 len= 16 +module rrc_coeff_ram_generated0_0 (input clock, input strobe, input [3:0] phase, input [4:0] in_data, output [15:0] out_data,output [17:0] ext_out_data); + +reg reg_quadrant; +wire quadrant=in_data[4]; +wire [7:0] rd_addr={phase,quadrant?~in_data[3:0]:in_data[3:0]}; +reg [15:0] rd_data; + + always @(posedge clock) + if (strobe) + begin + reg_quadrant <= #1 quadrant; + case (rd_addr) + 8'd0 : rd_data <= #1 -16'd12073; + 8'd1 : rd_data <= #1 -16'd12638; + 8'd2 : rd_data <= #1 -16'd11607; + 8'd3 : rd_data <= #1 -16'd12173; + 8'd4 : rd_data <= #1 -16'd10826; + 8'd5 : rd_data <= #1 -16'd11392; + 8'd6 : rd_data <= #1 -16'd10360; + 8'd7 : rd_data <= #1 -16'd10926; + 8'd8 : rd_data <= #1 -16'd18650; + 8'd9 : rd_data <= #1 -16'd19216; + 8'd10 : rd_data <= #1 -16'd18184; + 8'd11 : rd_data <= #1 -16'd18750; + 8'd12 : rd_data <= #1 -16'd17404; + 8'd13 : rd_data <= #1 -16'd17970; + 8'd14 : rd_data <= #1 -16'd16938; + 8'd15 : rd_data <= #1 -16'd17504; + 8'd16 : rd_data <= #1 -16'd10056; + 8'd17 : rd_data <= #1 -16'd10543; + 8'd18 : rd_data <= #1 -16'd9458; + 8'd19 : rd_data <= #1 -16'd9945; + 8'd20 : rd_data <= #1 -16'd9381; + 8'd21 : rd_data <= #1 -16'd9868; + 8'd22 : rd_data <= #1 -16'd8783; + 8'd23 : rd_data <= #1 -16'd9270; + 8'd24 : rd_data <= #1 -16'd15321; + 8'd25 : rd_data <= #1 -16'd15809; + 8'd26 : rd_data <= #1 -16'd14724; + 8'd27 : rd_data <= #1 -16'd15211; + 8'd28 : rd_data <= #1 -16'd14647; + 8'd29 : rd_data <= #1 -16'd15134; + 8'd30 : rd_data <= #1 -16'd14049; + 8'd31 : rd_data <= #1 -16'd14536; + 8'd32 : rd_data <= #1 -16'd8081; + 8'd33 : rd_data <= #1 -16'd8461; + 8'd34 : rd_data <= #1 -16'd7408; + 8'd35 : rd_data <= #1 -16'd7789; + 8'd36 : rd_data <= #1 -16'd7942; + 8'd37 : rd_data <= #1 -16'd8323; + 8'd38 : rd_data <= #1 -16'd7270; + 8'd39 : rd_data <= #1 -16'd7650; + 8'd40 : rd_data <= #1 -16'd11940; + 8'd41 : rd_data <= #1 -16'd12321; + 8'd42 : rd_data <= #1 -16'd11268; + 8'd43 : rd_data <= #1 -16'd11648; + 8'd44 : rd_data <= #1 -16'd11802; + 8'd45 : rd_data <= #1 -16'd12182; + 8'd46 : rd_data <= #1 -16'd11129; + 8'd47 : rd_data <= #1 -16'd11510; + 8'd48 : rd_data <= #1 -16'd6185; + 8'd49 : rd_data <= #1 -16'd6439; + 8'd50 : rd_data <= #1 -16'd5497; + 8'd51 : rd_data <= #1 -16'd5751; + 8'd52 : rd_data <= #1 -16'd6518; + 8'd53 : rd_data <= #1 -16'd6772; + 8'd54 : rd_data <= #1 -16'd5830; + 8'd55 : rd_data <= #1 -16'd6084; + 8'd56 : rd_data <= #1 -16'd8624; + 8'd57 : rd_data <= #1 -16'd8877; + 8'd58 : rd_data <= #1 -16'd7935; + 8'd59 : rd_data <= #1 -16'd8189; + 8'd60 : rd_data <= #1 -16'd8956; + 8'd61 : rd_data <= #1 -16'd9210; + 8'd62 : rd_data <= #1 -16'd8268; + 8'd63 : rd_data <= #1 -16'd8522; + 8'd64 : rd_data <= #1 -16'd4403; + 8'd65 : rd_data <= #1 -16'd4519; + 8'd66 : rd_data <= #1 -16'd3755; + 8'd67 : rd_data <= #1 -16'd3871; + 8'd68 : rd_data <= #1 -16'd5122; + 8'd69 : rd_data <= #1 -16'd5238; + 8'd70 : rd_data <= #1 -16'd4474; + 8'd71 : rd_data <= #1 -16'd4590; + 8'd72 : rd_data <= #1 -16'd5477; + 8'd73 : rd_data <= #1 -16'd5593; + 8'd74 : rd_data <= #1 -16'd4829; + 8'd75 : rd_data <= #1 -16'd4945; + 8'd76 : rd_data <= #1 -16'd6196; + 8'd77 : rd_data <= #1 -16'd6312; + 8'd78 : rd_data <= #1 -16'd5548; + 8'd79 : rd_data <= #1 -16'd5664; + 8'd80 : rd_data <= #1 -16'd2765; + 8'd81 : rd_data <= #1 -16'd2741; + 8'd82 : rd_data <= #1 -16'd2206; + 8'd83 : rd_data <= #1 -16'd2182; + 8'd84 : rd_data <= #1 -16'd3771; + 8'd85 : rd_data <= #1 -16'd3747; + 8'd86 : rd_data <= #1 -16'd3212; + 8'd87 : rd_data <= #1 -16'd3188; + 8'd88 : rd_data <= #1 -16'd2593; + 8'd89 : rd_data <= #1 -16'd2570; + 8'd90 : rd_data <= #1 -16'd2034; + 8'd91 : rd_data <= #1 -16'd2011; + 8'd92 : rd_data <= #1 -16'd3599; + 8'd93 : rd_data <= #1 -16'd3575; + 8'd94 : rd_data <= #1 -16'd3040; + 8'd95 : rd_data <= #1 -16'd3016; + 8'd96 : rd_data <= #1 -16'd1296; + 8'd97 : rd_data <= #1 -16'd1141; + 8'd98 : rd_data <= #1 -16'd866; + 8'd99 : rd_data <= #1 -16'd711; + 8'd100 : rd_data <= #1 -16'd2483; + 8'd101 : rd_data <= #1 -16'd2327; + 8'd102 : rd_data <= #1 -16'd2053; + 8'd103 : rd_data <= #1 -16'd1897; + 8'd104 : rd_data <= #1 -16'd46; + 8'd105 : rd_data <= #1 16'd110; + 8'd106 : rd_data <= #1 16'd384; + 8'd107 : rd_data <= #1 16'd540; + 8'd108 : rd_data <= #1 -16'd1232; + 8'd109 : rd_data <= #1 -16'd1077; + 8'd110 : rd_data <= #1 -16'd802; + 8'd111 : rd_data <= #1 -16'd647; + 8'd112 : rd_data <= #1 -16'd17; + 8'd113 : rd_data <= #1 16'd254; + 8'd114 : rd_data <= #1 16'd255; + 8'd115 : rd_data <= #1 16'd527; + 8'd116 : rd_data <= #1 -16'd1279; + 8'd117 : rd_data <= #1 -16'd1008; + 8'd118 : rd_data <= #1 -16'd1007; + 8'd119 : rd_data <= #1 -16'd735; + 8'd120 : rd_data <= #1 16'd2110; + 8'd121 : rd_data <= #1 16'd2381; + 8'd122 : rd_data <= #1 16'd2382; + 8'd123 : rd_data <= #1 16'd2654; + 8'd124 : rd_data <= #1 16'd848; + 8'd125 : rd_data <= #1 16'd1119; + 8'd126 : rd_data <= #1 16'd1120; + 8'd127 : rd_data <= #1 16'd1392; + 8'd128 : rd_data <= #1 16'd1058; + 8'd129 : rd_data <= #1 16'd1423; + 8'd130 : rd_data <= #1 16'd1157; + 8'd131 : rd_data <= #1 16'd1522; + 8'd132 : rd_data <= #1 -16'd181; + 8'd133 : rd_data <= #1 16'd184; + 8'd134 : rd_data <= #1 -16'd81; + 8'd135 : rd_data <= #1 16'd284; + 8'd136 : rd_data <= #1 16'd3838; + 8'd137 : rd_data <= #1 16'd4203; + 8'd138 : rd_data <= #1 16'd3937; + 8'd139 : rd_data <= #1 16'd4302; + 8'd140 : rd_data <= #1 16'd2599; + 8'd141 : rd_data <= #1 16'd2964; + 8'd142 : rd_data <= #1 16'd2698; + 8'd143 : rd_data <= #1 16'd3063; + 8'd144 : rd_data <= #1 16'd1921; + 8'd145 : rd_data <= #1 16'd2353; + 8'd146 : rd_data <= #1 16'd1845; + 8'd147 : rd_data <= #1 16'd2277; + 8'd148 : rd_data <= #1 16'd792; + 8'd149 : rd_data <= #1 16'd1223; + 8'd150 : rd_data <= #1 16'd716; + 8'd151 : rd_data <= #1 16'd1147; + 8'd152 : rd_data <= #1 16'd5122; + 8'd153 : rd_data <= #1 16'd5553; + 8'd154 : rd_data <= #1 16'd5046; + 8'd155 : rd_data <= #1 16'd5477; + 8'd156 : rd_data <= #1 16'd3993; + 8'd157 : rd_data <= #1 16'd4424; + 8'd158 : rd_data <= #1 16'd3917; + 8'd159 : rd_data <= #1 16'd4348; + 8'd160 : rd_data <= #1 16'd2572; + 8'd161 : rd_data <= #1 16'd3039; + 8'd162 : rd_data <= #1 16'd2330; + 8'd163 : rd_data <= #1 16'd2797; + 8'd164 : rd_data <= #1 16'd1621; + 8'd165 : rd_data <= #1 16'd2088; + 8'd166 : rd_data <= #1 16'd1379; + 8'd167 : rd_data <= #1 16'd1847; + 8'd168 : rd_data <= #1 16'd5967; + 8'd169 : rd_data <= #1 16'd6434; + 8'd170 : rd_data <= #1 16'd5726; + 8'd171 : rd_data <= #1 16'd6193; + 8'd172 : rd_data <= #1 16'd5016; + 8'd173 : rd_data <= #1 16'd5484; + 8'd174 : rd_data <= #1 16'd4775; + 8'd175 : rd_data <= #1 16'd5242; + 8'd176 : rd_data <= #1 16'd3014; + 8'd177 : rd_data <= #1 16'd3486; + 8'd178 : rd_data <= #1 16'd2628; + 8'd179 : rd_data <= #1 16'd3100; + 8'd180 : rd_data <= #1 16'd2291; + 8'd181 : rd_data <= #1 16'd2764; + 8'd182 : rd_data <= #1 16'd1906; + 8'd183 : rd_data <= #1 16'd2378; + 8'd184 : rd_data <= #1 16'd6394; + 8'd185 : rd_data <= #1 16'd6866; + 8'd186 : rd_data <= #1 16'd6008; + 8'd187 : rd_data <= #1 16'd6480; + 8'd188 : rd_data <= #1 16'd5671; + 8'd189 : rd_data <= #1 16'd6144; + 8'd190 : rd_data <= #1 16'd5286; + 8'd191 : rd_data <= #1 16'd5758; + 8'd192 : rd_data <= #1 16'd3258; + 8'd193 : rd_data <= #1 16'd3706; + 8'd194 : rd_data <= #1 16'd2759; + 8'd195 : rd_data <= #1 16'd3206; + 8'd196 : rd_data <= #1 16'd2794; + 8'd197 : rd_data <= #1 16'd3241; + 8'd198 : rd_data <= #1 16'd2294; + 8'd199 : rd_data <= #1 16'd2741; + 8'd200 : rd_data <= #1 16'd6438; + 8'd201 : rd_data <= #1 16'd6886; + 8'd202 : rd_data <= #1 16'd5939; + 8'd203 : rd_data <= #1 16'd6386; + 8'd204 : rd_data <= #1 16'd5974; + 8'd205 : rd_data <= #1 16'd6421; + 8'd206 : rd_data <= #1 16'd5474; + 8'd207 : rd_data <= #1 16'd5921; + 8'd208 : rd_data <= #1 16'd3322; + 8'd209 : rd_data <= #1 16'd3718; + 8'd210 : rd_data <= #1 16'd2745; + 8'd211 : rd_data <= #1 16'd3140; + 8'd212 : rd_data <= #1 16'd3123; + 8'd213 : rd_data <= #1 16'd3519; + 8'd214 : rd_data <= #1 16'd2546; + 8'd215 : rd_data <= #1 16'd2942; + 8'd216 : rd_data <= #1 16'd6150; + 8'd217 : rd_data <= #1 16'd6546; + 8'd218 : rd_data <= #1 16'd5573; + 8'd219 : rd_data <= #1 16'd5969; + 8'd220 : rd_data <= #1 16'd5951; + 8'd221 : rd_data <= #1 16'd6347; + 8'd222 : rd_data <= #1 16'd5374; + 8'd223 : rd_data <= #1 16'd5770; + 8'd224 : rd_data <= #1 16'd3225; + 8'd225 : rd_data <= #1 16'd3547; + 8'd226 : rd_data <= #1 16'd2611; + 8'd227 : rd_data <= #1 16'd2933; + 8'd228 : rd_data <= #1 16'd3281; + 8'd229 : rd_data <= #1 16'd3603; + 8'd230 : rd_data <= #1 16'd2667; + 8'd231 : rd_data <= #1 16'd2989; + 8'd232 : rd_data <= #1 16'd5587; + 8'd233 : rd_data <= #1 16'd5909; + 8'd234 : rd_data <= #1 16'd4973; + 8'd235 : rd_data <= #1 16'd5295; + 8'd236 : rd_data <= #1 16'd5643; + 8'd237 : rd_data <= #1 16'd5965; + 8'd238 : rd_data <= #1 16'd5029; + 8'd239 : rd_data <= #1 16'd5351; + 8'd240 : rd_data <= #1 16'd2992; + 8'd241 : rd_data <= #1 16'd3224; + 8'd242 : rd_data <= #1 16'd2382; + 8'd243 : rd_data <= #1 16'd2615; + 8'd244 : rd_data <= #1 16'd3274; + 8'd245 : rd_data <= #1 16'd3506; + 8'd246 : rd_data <= #1 16'd2664; + 8'd247 : rd_data <= #1 16'd2896; + 8'd248 : rd_data <= #1 16'd4813; + 8'd249 : rd_data <= #1 16'd5046; + 8'd250 : rd_data <= #1 16'd4204; + 8'd251 : rd_data <= #1 16'd4436; + 8'd252 : rd_data <= #1 16'd5095; + 8'd253 : rd_data <= #1 16'd5328; + 8'd254 : rd_data <= #1 16'd4486; + 8'd255 : rd_data <= #1 16'd4718; + endcase // case(rd_addr) + end //if (strobe) + assign out_data[15:0]=reg_quadrant?-rd_data:rd_data; + sign_extend #(16,18) + ext_output (.in(out_data),.out(ext_out_data)); + +endmodule // rrc_coeff_ram_generated_0 + +//bw= 16 data_size= 5 abs_max= 32767 len= 16 +module rrc_coeff_ram_generated0_1 (input clock, input strobe, input [3:0] phase, input [4:0] in_data, output [15:0] out_data,output [17:0] ext_out_data); + +reg reg_quadrant; +wire quadrant=in_data[4]; +wire [7:0] rd_addr={phase,quadrant?~in_data[3:0]:in_data[3:0]}; +reg [15:0] rd_data; + + always @(posedge clock) + if (strobe) + begin + reg_quadrant <= #1 quadrant; + case (rd_addr) + 8'd0 : rd_data <= #1 -16'd12073; + 8'd1 : rd_data <= #1 16'd17504; + 8'd2 : rd_data <= #1 -16'd18650; + 8'd3 : rd_data <= #1 16'd10926; + 8'd4 : rd_data <= #1 -16'd10826; + 8'd5 : rd_data <= #1 16'd18750; + 8'd6 : rd_data <= #1 -16'd17404; + 8'd7 : rd_data <= #1 16'd12173; + 8'd8 : rd_data <= #1 -16'd11607; + 8'd9 : rd_data <= #1 16'd17970; + 8'd10 : rd_data <= #1 -16'd18184; + 8'd11 : rd_data <= #1 16'd11392; + 8'd12 : rd_data <= #1 -16'd10360; + 8'd13 : rd_data <= #1 16'd19216; + 8'd14 : rd_data <= #1 -16'd16938; + 8'd15 : rd_data <= #1 16'd12638; + 8'd16 : rd_data <= #1 -16'd14094; + 8'd17 : rd_data <= #1 16'd20310; + 8'd18 : rd_data <= #1 -16'd21804; + 8'd19 : rd_data <= #1 16'd12600; + 8'd20 : rd_data <= #1 -16'd12273; + 8'd21 : rd_data <= #1 16'd22132; + 8'd22 : rd_data <= #1 -16'd19982; + 8'd23 : rd_data <= #1 16'd14422; + 8'd24 : rd_data <= #1 -16'd13812; + 8'd25 : rd_data <= #1 16'd20592; + 8'd26 : rd_data <= #1 -16'd21522; + 8'd27 : rd_data <= #1 16'd12882; + 8'd28 : rd_data <= #1 -16'd11991; + 8'd29 : rd_data <= #1 16'd22413; + 8'd30 : rd_data <= #1 -16'd19700; + 8'd31 : rd_data <= #1 16'd14704; + 8'd32 : rd_data <= #1 -16'd16081; + 8'd33 : rd_data <= #1 16'd22854; + 8'd34 : rd_data <= #1 -16'd24657; + 8'd35 : rd_data <= #1 16'd14278; + 8'd36 : rd_data <= #1 -16'd13719; + 8'd37 : rd_data <= #1 16'd25216; + 8'd38 : rd_data <= #1 -16'd22295; + 8'd39 : rd_data <= #1 16'd16640; + 8'd40 : rd_data <= #1 -16'd16026; + 8'd41 : rd_data <= #1 16'd22909; + 8'd42 : rd_data <= #1 -16'd24602; + 8'd43 : rd_data <= #1 16'd14333; + 8'd44 : rd_data <= #1 -16'd13664; + 8'd45 : rd_data <= #1 16'd25271; + 8'd46 : rd_data <= #1 -16'd22240; + 8'd47 : rd_data <= #1 16'd16695; + 8'd48 : rd_data <= #1 -16'd17997; + 8'd49 : rd_data <= #1 16'd25037; + 8'd50 : rd_data <= #1 -16'd27089; + 8'd51 : rd_data <= #1 16'd15945; + 8'd52 : rd_data <= #1 -16'd15169; + 8'd53 : rd_data <= #1 16'd27865; + 8'd54 : rd_data <= #1 -16'd24261; + 8'd55 : rd_data <= #1 16'd18773; + 8'd56 : rd_data <= #1 -16'd18196; + 8'd57 : rd_data <= #1 16'd24838; + 8'd58 : rd_data <= #1 -16'd27288; + 8'd59 : rd_data <= #1 16'd15746; + 8'd60 : rd_data <= #1 -16'd15368; + 8'd61 : rd_data <= #1 16'd27666; + 8'd62 : rd_data <= #1 -16'd24460; + 8'd63 : rd_data <= #1 16'd18574; + 8'd64 : rd_data <= #1 -16'd19806; + 8'd65 : rd_data <= #1 16'd26771; + 8'd66 : rd_data <= #1 -16'd28986; + 8'd67 : rd_data <= #1 16'd17591; + 8'd68 : rd_data <= #1 -16'd16627; + 8'd69 : rd_data <= #1 16'd29951; + 8'd70 : rd_data <= #1 -16'd25806; + 8'd71 : rd_data <= #1 16'd20771; + 8'd72 : rd_data <= #1 -16'd20271; + 8'd73 : rd_data <= #1 16'd26306; + 8'd74 : rd_data <= #1 -16'd29451; + 8'd75 : rd_data <= #1 16'd17126; + 8'd76 : rd_data <= #1 -16'd17091; + 8'd77 : rd_data <= #1 16'd29486; + 8'd78 : rd_data <= #1 -16'd26271; + 8'd79 : rd_data <= #1 16'd20306; + 8'd80 : rd_data <= #1 -16'd21478; + 8'd81 : rd_data <= #1 16'd27977; + 8'd82 : rd_data <= #1 -16'd30249; + 8'd83 : rd_data <= #1 16'd19206; + 8'd84 : rd_data <= #1 -16'd18098; + 8'd85 : rd_data <= #1 16'd31357; + 8'd86 : rd_data <= #1 -16'd26869; + 8'd87 : rd_data <= #1 16'd22586; + 8'd88 : rd_data <= #1 -16'd22200; + 8'd89 : rd_data <= #1 16'd27255; + 8'd90 : rd_data <= #1 -16'd30972; + 8'd91 : rd_data <= #1 16'd18483; + 8'd92 : rd_data <= #1 -16'd18820; + 8'd93 : rd_data <= #1 16'd30635; + 8'd94 : rd_data <= #1 -16'd27592; + 8'd95 : rd_data <= #1 16'd21863; + 8'd96 : rd_data <= #1 -16'd22984; + 8'd97 : rd_data <= #1 16'd28594; + 8'd98 : rd_data <= #1 -16'd30797; + 8'd99 : rd_data <= #1 16'd20781; + 8'd100 : rd_data <= #1 -16'd19588; + 8'd101 : rd_data <= #1 16'd31990; + 8'd102 : rd_data <= #1 -16'd27402; + 8'd103 : rd_data <= #1 16'd24176; + 8'd104 : rd_data <= #1 -16'd23935; + 8'd105 : rd_data <= #1 16'd27643; + 8'd106 : rd_data <= #1 -16'd31748; + 8'd107 : rd_data <= #1 16'd19830; + 8'd108 : rd_data <= #1 -16'd20539; + 8'd109 : rd_data <= #1 16'd31039; + 8'd110 : rd_data <= #1 -16'd28353; + 8'd111 : rd_data <= #1 16'd23225; + 8'd112 : rd_data <= #1 -16'd24303; + 8'd113 : rd_data <= #1 16'd28577; + 8'd114 : rd_data <= #1 -16'd30572; + 8'd115 : rd_data <= #1 16'd22307; + 8'd116 : rd_data <= #1 -16'd21102; + 8'd117 : rd_data <= #1 16'd31777; + 8'd118 : rd_data <= #1 -16'd27371; + 8'd119 : rd_data <= #1 16'd25508; + 8'd120 : rd_data <= #1 -16'd25432; + 8'd121 : rd_data <= #1 16'd27447; + 8'd122 : rd_data <= #1 -16'd31701; + 8'd123 : rd_data <= #1 16'd21178; + 8'd124 : rd_data <= #1 -16'd22231; + 8'd125 : rd_data <= #1 16'd30648; + 8'd126 : rd_data <= #1 -16'd28500; + 8'd127 : rd_data <= #1 16'd24379; + 8'd128 : rd_data <= #1 -16'd25418; + 8'd129 : rd_data <= #1 16'd27899; + 8'd130 : rd_data <= #1 -16'd29540; + 8'd131 : rd_data <= #1 16'd23778; + 8'd132 : rd_data <= #1 -16'd22639; + 8'd133 : rd_data <= #1 16'd30679; + 8'd134 : rd_data <= #1 -16'd26760; + 8'd135 : rd_data <= #1 16'd26557; + 8'd136 : rd_data <= #1 -16'd26657; + 8'd137 : rd_data <= #1 16'd26661; + 8'd138 : rd_data <= #1 -16'd30778; + 8'd139 : rd_data <= #1 16'd22539; + 8'd140 : rd_data <= #1 -16'd23877; + 8'd141 : rd_data <= #1 16'd29440; + 8'd142 : rd_data <= #1 -16'd27999; + 8'd143 : rd_data <= #1 16'd25319; + 8'd144 : rd_data <= #1 -16'd26321; + 8'd145 : rd_data <= #1 16'd26558; + 8'd146 : rd_data <= #1 -16'd27696; + 8'd147 : rd_data <= #1 16'd25183; + 8'd148 : rd_data <= #1 -16'd24194; + 8'd149 : rd_data <= #1 16'd28685; + 8'd150 : rd_data <= #1 -16'd25569; + 8'd151 : rd_data <= #1 16'd27310; + 8'd152 : rd_data <= #1 -16'd27583; + 8'd153 : rd_data <= #1 16'd25296; + 8'd154 : rd_data <= #1 -16'd28957; + 8'd155 : rd_data <= #1 16'd23922; + 8'd156 : rd_data <= #1 -16'd25456; + 8'd157 : rd_data <= #1 16'd27423; + 8'd158 : rd_data <= #1 -16'd26830; + 8'd159 : rd_data <= #1 16'd26049; + 8'd160 : rd_data <= #1 -16'd27007; + 8'd161 : rd_data <= #1 16'd24570; + 8'd162 : rd_data <= #1 -16'd25064; + 8'd163 : rd_data <= #1 16'd26514; + 8'd164 : rd_data <= #1 -16'd25757; + 8'd165 : rd_data <= #1 16'd25821; + 8'd166 : rd_data <= #1 -16'd23814; + 8'd167 : rd_data <= #1 16'd27764; + 8'd168 : rd_data <= #1 -16'd28194; + 8'd169 : rd_data <= #1 16'd23384; + 8'd170 : rd_data <= #1 -16'd26251; + 8'd171 : rd_data <= #1 16'd25327; + 8'd172 : rd_data <= #1 -16'd26943; + 8'd173 : rd_data <= #1 16'd24634; + 8'd174 : rd_data <= #1 -16'd25000; + 8'd175 : rd_data <= #1 16'd26578; + 8'd176 : rd_data <= #1 -16'd27481; + 8'd177 : rd_data <= #1 16'd21974; + 8'd178 : rd_data <= #1 -16'd21699; + 8'd179 : rd_data <= #1 16'd27756; + 8'd180 : rd_data <= #1 -16'd27309; + 8'd181 : rd_data <= #1 16'd22146; + 8'd182 : rd_data <= #1 -16'd21528; + 8'd183 : rd_data <= #1 16'd27927; + 8'd184 : rd_data <= #1 -16'd28486; + 8'd185 : rd_data <= #1 16'd20969; + 8'd186 : rd_data <= #1 -16'd22705; + 8'd187 : rd_data <= #1 16'd26750; + 8'd188 : rd_data <= #1 -16'd28315; + 8'd189 : rd_data <= #1 16'd21140; + 8'd190 : rd_data <= #1 -16'd22533; + 8'd191 : rd_data <= #1 16'd26922; + 8'd192 : rd_data <= #1 -16'd27750; + 8'd193 : rd_data <= #1 16'd18827; + 8'd194 : rd_data <= #1 -16'd17683; + 8'd195 : rd_data <= #1 16'd28895; + 8'd196 : rd_data <= #1 -16'd28824; + 8'd197 : rd_data <= #1 16'd17753; + 8'd198 : rd_data <= #1 -16'd18757; + 8'd199 : rd_data <= #1 16'd27820; + 8'd200 : rd_data <= #1 -16'd28469; + 8'd201 : rd_data <= #1 16'd18108; + 8'd202 : rd_data <= #1 -16'd18402; + 8'd203 : rd_data <= #1 16'd28176; + 8'd204 : rd_data <= #1 -16'd29543; + 8'd205 : rd_data <= #1 16'd17034; + 8'd206 : rd_data <= #1 -16'd19476; + 8'd207 : rd_data <= #1 16'd27101; + 8'd208 : rd_data <= #1 -16'd27829; + 8'd209 : rd_data <= #1 16'd15205; + 8'd210 : rd_data <= #1 -16'd13122; + 8'd211 : rd_data <= #1 16'd29912; + 8'd212 : rd_data <= #1 -16'd30267; + 8'd213 : rd_data <= #1 16'd12767; + 8'd214 : rd_data <= #1 -16'd15560; + 8'd215 : rd_data <= #1 16'd27474; + 8'd216 : rd_data <= #1 -16'd28162; + 8'd217 : rd_data <= #1 16'd14872; + 8'd218 : rd_data <= #1 -16'd13455; + 8'd219 : rd_data <= #1 16'd29579; + 8'd220 : rd_data <= #1 -16'd30600; + 8'd221 : rd_data <= #1 16'd12434; + 8'd222 : rd_data <= #1 -16'd15893; + 8'd223 : rd_data <= #1 16'd27141; + 8'd224 : rd_data <= #1 -16'd27738; + 8'd225 : rd_data <= #1 16'd11197; + 8'd226 : rd_data <= #1 -16'd8148; + 8'd227 : rd_data <= #1 16'd30787; + 8'd228 : rd_data <= #1 -16'd31598; + 8'd229 : rd_data <= #1 16'd7337; + 8'd230 : rd_data <= #1 -16'd12008; + 8'd231 : rd_data <= #1 16'd26927; + 8'd232 : rd_data <= #1 -16'd27600; + 8'd233 : rd_data <= #1 16'd11335; + 8'd234 : rd_data <= #1 -16'd8009; + 8'd235 : rd_data <= #1 16'd30926; + 8'd236 : rd_data <= #1 -16'd31459; + 8'd237 : rd_data <= #1 16'd7476; + 8'd238 : rd_data <= #1 -16'd11869; + 8'd239 : rd_data <= #1 16'd27066; + 8'd240 : rd_data <= #1 -16'd27501; + 8'd241 : rd_data <= #1 16'd6903; + 8'd242 : rd_data <= #1 -16'd2909; + 8'd243 : rd_data <= #1 16'd31495; + 8'd244 : rd_data <= #1 -16'd32767; + 8'd245 : rd_data <= #1 16'd1637; + 8'd246 : rd_data <= #1 -16'd8175; + 8'd247 : rd_data <= #1 16'd26229; + 8'd248 : rd_data <= #1 -16'd26827; + 8'd249 : rd_data <= #1 16'd7577; + 8'd250 : rd_data <= #1 -16'd2235; + 8'd251 : rd_data <= #1 16'd32169; + 8'd252 : rd_data <= #1 -16'd32093; + 8'd253 : rd_data <= #1 16'd2312; + 8'd254 : rd_data <= #1 -16'd7501; + 8'd255 : rd_data <= #1 16'd26903; + endcase // case(rd_addr) + end //if (strobe) + assign out_data[15:0]=reg_quadrant?-rd_data:rd_data; + sign_extend #(16,18) + ext_output (.in(out_data),.out(ext_out_data)); + +endmodule // rrc_coeff_ram_generated_1 + +//bw= 9 data_size= 1 abs_max= 244 len= 1 +module rrc_coeff_ram_generated0_2 (input clock, input strobe, input [3:0] phase, input [0:0] in_data, output [8:0] out_data,output [17:0] ext_out_data); + +reg reg_quadrant; +wire quadrant=in_data[0]; +wire [3:0] rd_addr=phase; +reg [8:0] rd_data; + + always @(posedge clock) + if (strobe) + begin + reg_quadrant <= #1 quadrant; + case (rd_addr) + 4'd0 : rd_data <= #1 -9'd67; + 4'd1 : rd_data <= #1 -9'd116; + 4'd2 : rd_data <= #1 -9'd161; + 4'd3 : rd_data <= #1 -9'd198; + 4'd4 : rd_data <= #1 -9'd224; + 4'd5 : rd_data <= #1 -9'd236; + 4'd6 : rd_data <= #1 -9'd234; + 4'd7 : rd_data <= #1 -9'd216; + 4'd8 : rd_data <= #1 -9'd183; + 4'd9 : rd_data <= #1 -9'd136; + 4'd10 : rd_data <= #1 -9'd78; + 4'd11 : rd_data <= #1 -9'd12; + 4'd12 : rd_data <= #1 9'd58; + 4'd13 : rd_data <= #1 9'd127; + 4'd14 : rd_data <= #1 9'd190; + 4'd15 : rd_data <= #1 9'd244; + endcase // case(rd_addr) + end //if (strobe) + assign out_data[8:0]=reg_quadrant?-rd_data:rd_data; + sign_extend #(9,18) + ext_output (.in(out_data),.out(ext_out_data)); + +endmodule // rrc_coeff_ram_generated_2 + +//bw_memory [4, 4, 0] data_size 5 +module frac_interp_0 + + (input clock, input reset, input enable, + output reg strobe_in, input strobe_out, + input wire [4:0] tx_shift, + input wire [15:0] signal_in, + output reg [15:0] signal_out); + +reg [3:0] phase;//max 16 phases + +reg [3:0] in_count;//16 bits in every register + +reg [15:0] input_16; + +reg [15:0] shift_16_0; +wire get_bit= (phase==4'd15); + + always @(posedge clock) + if (reset) + begin + strobe_in <= #1 0;// Reset + in_count <=#1 0; + input_16 <= #1 0; + + shift_16_0 <= #1 0; + + end //if (reset) + else //if (reset) + begin + if(enable & strobe_out & get_bit & (in_count == 4'd15)) + strobe_in <=#1 1'd1;//Only works if output of previous stage is registered and only updates on this strobe_in + else // if(strobe_in) //input a new 16 bit word and shift all regs 16 bit to the right= to next register) + strobe_in <= #1 0;//notice the else is always executed, even if there is no strobe_out so strobe_in will only be high for 1 clock + + if (enable & strobe_out) + begin + if ( get_bit) + + begin //shift input 1 bit to the left + if(in_count == 4'd15) //(strobe_in) //if(in_count == 4'd0) + begin + //strobe_in <=#1 1'd1;//Only works if output of previous stage is registered and only updates on this strobe_in + input_16 <= #1 signal_in; + end //if(in_count == 4'd0) + else //if(in_count == 4'd0) + begin + input_16 <= #1 {1'd0,input_16[15:1]};//just shift right //MDVH 14feb2007 + //input_16 <= #1 {input_16[14:0],1'd0};//just shift left //MDVH 14feb2007 + end // if(in_count == 4'd0) else + //shift_16_0 <= #1 {shift_16_0[14:0],input_16[15]};//MDVH 14feb2007 + shift_16_0 <= #1 {input_16[0],shift_16_0[15:1]};//MDVH 14feb2007 + + + in_count <= #1 in_count+4'd1; + end //if ((phase==.... + end //if (enable & strobe_out) + end // if (reset) else + + always @(posedge clock) + if (reset) + phase <=#1 0; + else if (enable & strobe_out) + phase <=#1 phase + 4'd1;//phase will roll-over to zero and start again + + +wire [4:0] data_0; +wire [4:0] data_1; +wire [0:0] data_2; +assign data_2=shift_16_0[10:10]; +assign data_1=shift_16_0[9:5]; +assign data_0=shift_16_0[4:0]; +wire [17:0] sum_0; +wire [17:0] sum_1; +wire [17:0] sum_2; +wire [17:0] sum_3; +assign sum_3=0; +reg [17:0] sum_all; + +//wire [15:0] sum_all_16bit; + + rrc_coeff_ram_generated0_0 rrc_coeff_ram_0 ( .clock(clock),.strobe(strobe_out),.phase(phase),.in_data(data_0),.out_data(),.ext_out_data(sum_0) ); + rrc_coeff_ram_generated0_1 rrc_coeff_ram_1 ( .clock(clock),.strobe(strobe_out),.phase(phase),.in_data(data_1),.out_data(),.ext_out_data(sum_1) ); + rrc_coeff_ram_generated0_2 rrc_coeff_ram_2 ( .clock(clock),.strobe(strobe_out),.phase(phase),.in_data(data_2),.out_data(),.ext_out_data(sum_2) ); +//assign sum_all= sum_0 + sum_1 + sum_2; +reg [17:0] sum_01; +reg [17:0] sum_23; +reg [17:0] sum_0123; + + always @(posedge clock) + if (reset) + begin + + sum_01 <= #1 0; + sum_23 <= #1 0; + sum_0123 <= #1 0; + + sum_all <=#1 0; + signal_out <= #1 0; + end + else if (enable & strobe_out) + begin + + sum_01 <= #1 sum_0+sum_1; + sum_23 <= #1 sum_2+sum_3; + sum_0123 <= #1 sum_01+sum_23; + sum_all <= #1 sum_0123; + + case(tx_shift) + //5'd0 : signal_out <= #1 round_16(sum_all);//no gain reduce + 5'd0 : signal_out <= #1 { sum_all[16:1] + (sum_all[17] & ( sum_all[0] )) }; + 5'd1 : signal_out <= #1 { sum_all[17:2] + (sum_all[17] & (|sum_all[1:0])) }; + 5'd2 : signal_out <= #1 { {{(1){sum_all[17]}}, sum_all[17:3]} + (sum_all[17] & (|sum_all[2:0])) }; + 5'd3 : signal_out <= #1 { {{(2){sum_all[17]}}, sum_all[17:4]} + (sum_all[17] & (|sum_all[3:0])) }; + 5'd4 : signal_out <= #1 { {{(3){sum_all[17]}}, sum_all[17:5]} + (sum_all[17] & (|sum_all[4:0])) }; + 5'd5 : signal_out <= #1 { {{(4){sum_all[17]}}, sum_all[17:6]} + (sum_all[17] & (|sum_all[5:0])) }; + 5'd6 : signal_out <= #1 { {{(5){sum_all[17]}}, sum_all[17:7]} + (sum_all[17] & (|sum_all[6:0])) }; + 5'd7 : signal_out <= #1 { {{(6){sum_all[17]}}, sum_all[17:8]} + (sum_all[17] & (|sum_all[7:0])) }; + 5'd8 : signal_out <= #1 { {{(7){sum_all[17]}}, sum_all[17:9]} + (sum_all[17] & (|sum_all[8:0])) }; + 5'd9 : signal_out <= #1 { {{(8){sum_all[17]}}, sum_all[17:10]} + (sum_all[17] & (|sum_all[9:0])) }; + 5'd10 : signal_out <= #1 { {{(9){sum_all[17]}},sum_all[17:11]} + (sum_all[17] & (|sum_all[10:0]))}; + 5'd11 : signal_out <= #1 { {{(10){sum_all[17]}},sum_all[17:12]} + (sum_all[17] & (|sum_all[11:0]))}; + 5'd12 : signal_out <= #1 { {{(11){sum_all[17]}},sum_all[17:13]} + (sum_all[17] & (|sum_all[12:0]))}; + 5'd13 : signal_out <= #1 { {{(12){sum_all[17]}},sum_all[17:14]} + (sum_all[17] & (|sum_all[13:0]))}; + 5'd14 : signal_out <= #1 { {{(13){sum_all[17]}},sum_all[17:15]} + (sum_all[17] & (|sum_all[14:0]))}; + 5'd15 : signal_out <= #1 { {{(14){sum_all[17]}},sum_all[17:16]} + (sum_all[17] & (|sum_all[15:0]))}; + + -5'd1 : signal_out <= #1 {sum_all[15:0] }; + -5'd2 : signal_out <= #1 {sum_all[14:0] ,{(1){1'b0}}}; + -5'd3 : signal_out <= #1 {sum_all[13:0] ,{(2){1'b0}}}; + -5'd4 : signal_out <= #1 {sum_all[12:0] ,{(3){1'b0}}}; + -5'd5 : signal_out <= #1 {sum_all[11:0] ,{(4){1'b0}}}; + -5'd6 : signal_out <= #1 {sum_all[10:0] ,{(5){1'b0}}}; + -5'd7 : signal_out <= #1 {sum_all[9:0] ,{(6){1'b0}}}; + -5'd8 : signal_out <= #1 {sum_all[8:0] ,{(7){1'b0}}}; + -5'd9 : signal_out <= #1 {sum_all[7:0] ,{(8){1'b0}}}; + -5'd10 : signal_out <= #1 {sum_all[6:0] ,{(9){1'b0}}}; + -5'd11 : signal_out <= #1 {sum_all[5:0] ,{(10){1'b0}}}; + -5'd12 : signal_out <= #1 {sum_all[4:0] ,{(11){1'b0}}}; + -5'd13 : signal_out <= #1 {sum_all[3:0] ,{(12){1'b0}}}; + -5'd14 : signal_out <= #1 {sum_all[2:0] ,{(13){1'b0}}}; + -5'd15 : signal_out <= #1 {sum_all[1:0] ,{(14){1'b0}}}; + + default : signal_out <= #1 { sum_all[16:1] + (sum_all[17] & ( sum_all[0] )) }; + //signal_out <= #1 { sum_all[17:2] + (sum_all[17] & (|sum_all[1:0])) }; + endcase // case(shift) + + //sum_all_14bit <= #1 sum_0123[16:3] + (sum_0123[16] & |sum_0123[2:0]);//round to 14 bit (reduce gain by 2 bit = 12 dB) + + //signal_out <= #1 round_16(sum_all);//no gain reduce + //signal_out <= #1 {{(2){sum_all_14bit[13]}},sum_all_14bit};//sign_extend to 16 bit (gain reduced by 2 bit = 12 dB) + + end //else if (enable & strobe_out) + + +/*assign sum_all_16bit=round_16(sum_all); +//register the output to ease timing of the DDR DAC output + always @(posedge clock or posedge reset) + if (reset) + signal_out <= #1 0; // Reset + else + signal_out <= #1 sum_all_16bit; +*/ +//round to 16 bit +// function [15:0] round_16; +// input [16:0] in_val; +// round_16 = in_val[16:1] + (in_val[16] & |in_val[0]);//round_16 = in_val[16:1] + (in_val[16] & in_val[0]) +// endfunction // round_16 + + +endmodule //module frac_interp_0 Index: usrp/fpga/sdr_lib/frac_interp_1.v =================================================================== --- usrp/fpga/sdr_lib/frac_interp_1.v (revision 0) +++ usrp/fpga/sdr_lib/frac_interp_1.v (revision 0) @@ -0,0 +1,879 @@ +// -*- verilog -*- +// +// Polyphase interpolating Root-Raised-Cosine filter +// +// Copyright (C) 2007 Martin Dudok van Heel +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// +// Polyphase interpolating Root-Raised-Cosine filter +// Interpolation ratio can be fractional (float) +// +// This file was generated by ./generate_frac_interp_05nov2007.py at 2007-11-08 00:15:22.897244 +// Written by Martin Dudok van Heel, 2007 +// Olifantasia +// +// Contact: http://www.olifantasia.com/gnuradio/contact.gif or nldudok1_olifantasia_com +// http://www.olifantasia.com +// +// This file can be used to build a special purpose firmware for the USRP +// USRP = Universal Software Radio Peripheral +// This special purpose firmware in combination with the GnuRadio framework can be used to create a high speed QPSK transmitter +// Depending on the decimation and interpolation factors used, the symbolrate can be from 2 to 20 Msymbols/sec +// The corresponding QPSK bitrate is 4 to 40 Mbit/sec +// alpha= 0.35 +// interpolation = 16.0 decimation= 1.0 interp_ratio= 16.0 decim_ratio= 0.0625 +// symbol rate = 2.0 Msymbol/sec +// QPSK bitrate = 4.0 Mbit/sec +// +//fractional ntaps 176.0 +//ntaps_per_filter= 11 +//nfilters= 16 +// s f incr d_mu ii oo step +// 0.0 0.0 0 0.0 0 0 0 +// 0.0625 0.0 0 0.0625 0 1 1 +// 0.125 0.0 0 0.125 0 2 2 +// 0.1875 0.0 0 0.1875 0 3 3 +// 0.25 0.0 0 0.25 0 4 4 +// 0.3125 0.0 0 0.3125 0 5 5 +// 0.375 0.0 0 0.375 0 6 6 +// 0.4375 0.0 0 0.4375 0 7 7 +// 0.5 0.0 0 0.5 0 8 8 +// 0.5625 0.0 0 0.5625 0 9 9 +// 0.625 0.0 0 0.625 0 10 10 +// 0.6875 0.0 0 0.6875 0 11 11 +// 0.75 0.0 0 0.75 0 12 12 +// 0.8125 0.0 0 0.8125 0 13 13 +// 0.875 0.0 0 0.875 0 14 14 +// 0.9375 0.0 0 0.9375 0 15 15 +//poly_filter[ 0 ] = +// [-0.011587695450775884, 0.009540331775325591, 0.025529243999645228, -0.13471163423240112, 0.60573900392913038, 0.60573900392913038, -0.13471163423240112, 0.025529243999645228, 0.009540331775325591, -0.011587695450775884, 0.0027409495713674546] + +//poly_filter[ 1 ] = +// [-0.0099778106805516343, 0.012243898388679795, 0.01381187210553937, -0.10784673839600598, 0.5036516325587086, 0.70461324036848649, -0.15789857108157021, 0.037306542075417615, 0.0057724100313517913, -0.012484351992881374, 0.0047621700874819917] + +//poly_filter[ 2 ] = +// [-0.0077900979459937601, 0.013770041692387745, 0.0028393004067138075, -0.079043142889963613, 0.40121981446161492, 0.79740634077856587, -0.17563700569215573, 0.048374957455653546, 0.0011409471925254001, -0.012575432872464706, 0.0065948029259533299] + +//poly_filter[ 3 ] = +// [-0.0051918884379789634, 0.014094235134993529, -0.0068180138195810215, -0.049936985728082653, 0.30120806330766442, 0.88135824274746832, -0.1862032652736608, 0.057919959029894712, -0.0040722547133090715, -0.011820412465814426, 0.0081011166648467508] + +//poly_filter[ 4 ] = +// [-0.002369808994513568, 0.013275670848030585, -0.014725700012165777, -0.021998743447974509, 0.20617867436174767, 0.95392185609796487, -0.18800158643030346, 0.065125644071244701, -0.0095171104656519498, -0.010236276383968073, 0.0091588581512722211] + +//poly_filter[ 5 ] = +// [0.00048347260723167232, 0.011447479369610835, -0.020597793357802315, 0.0035176129499998993, 0.11840454095660065, 1.0128613066927243, -0.17964431069970466, 0.069223183473694869, -0.014793509202544011, -0.0078995715847417682, 0.0096704811556829768] + +//poly_filter[ 6 ] = +// [0.0031822326226663175, 0.008802914171020677, -0.024299705383391313, 0.02561204350538385, 0.039796304923507324, 1.0563390719129626, -0.16002739061571231, 0.069540957150195037, -0.019474353322261367, -0.004944470036472381, 0.0095711139086369253] + +//poly_filter[ 7 ] = +// [0.0055595783615640876, 0.0055786140616833589, -0.025842360059079271, 0.0435614578372319, -0.028153407707346888, 1.0829881487676363, -0.12839743104636323, 0.065553728158199417, -0.023132255200493404, -0.0015567455703022638, 0.0088346592297861831] + +//poly_filter[ 8 ] = +// [0.0074775197590773203, 0.0020361698472420751, -0.025368464034228311, 0.05692809049980125, -0.084406752442248281, 1.0919660406286562, -0.084406752442248281, 0.05692809049980125, -0.025368464034228311, 0.0020361698472420751, 0.0074775197590773203] + +//poly_filter[ 9 ] = +// [0.0088346592297861831, -0.0015567455703022638, -0.023132255200493404, 0.065553728158199417, -0.12839743104636323, 1.0829881487676363, -0.028153407707346888, 0.0435614578372319, -0.025842360059079271, 0.0055786140616833589, 0.0055595783615640876] + +//poly_filter[ 10 ] = +// [0.0095711139086369253, -0.004944470036472381, -0.019474353322261367, 0.069540957150195037, -0.16002739061571231, 1.0563390719129626, 0.039796304923507324, 0.02561204350538385, -0.024299705383391313, 0.008802914171020677, 0.0031822326226663175] + +//poly_filter[ 11 ] = +// [0.0096704811556829768, -0.0078995715847417682, -0.014793509202544011, 0.069223183473694869, -0.17964431069970466, 1.0128613066927243, 0.11840454095660065, 0.0035176129499998993, -0.020597793357802315, 0.011447479369610835, 0.00048347260723167232] + +//poly_filter[ 12 ] = +// [0.0091588581512722211, -0.010236276383968073, -0.0095171104656519498, 0.065125644071244701, -0.18800158643030346, 0.95392185609796487, 0.20617867436174767, -0.021998743447974509, -0.014725700012165777, 0.013275670848030585, -0.002369808994513568] + +//poly_filter[ 13 ] = +// [0.0081011166648467508, -0.011820412465814426, -0.0040722547133090715, 0.057919959029894712, -0.1862032652736608, 0.88135824274746832, 0.30120806330766442, -0.049936985728082653, -0.0068180138195810215, 0.014094235134993529, -0.0051918884379789634] + +//poly_filter[ 14 ] = +// [0.0065948029259533299, -0.012575432872464706, 0.0011409471925254001, 0.048374957455653546, -0.17563700569215573, 0.79740634077856587, 0.40121981446161492, -0.079043142889963613, 0.0028393004067138075, 0.013770041692387745, -0.0077900979459937601] + +//poly_filter[ 15 ] = +// [0.0047621700874819917, -0.012484351992881374, 0.0057724100313517913, 0.037306542075417615, -0.15789857108157021, 0.70461324036848649, 0.5036516325587086, -0.10784673839600598, 0.01381187210553937, 0.012243898388679795, -0.0099778106805516343] + +// total_ntaps= 176 +// ntaps_per_filter= 11 +// nfilters= 16 +// filter resolution= 16 bits +// +//data_size= 5 phase_size= 4 +//abs_max= 1.34216738182 abs_max_16bit= 32767 signed_max_16bit= 32169 signed_min_16bit= -32767 +//nmemories= 3 +//incr_list = [15] +//bw= 16 data_size= 5 abs_max= 19216 len= 16 +module rrc_coeff_ram_generated1_0 (input clock, input strobe, input [3:0] phase, input [4:0] in_data, output [15:0] out_data,output [17:0] ext_out_data); + +reg reg_quadrant; +wire quadrant=in_data[4]; +wire [7:0] rd_addr={phase,quadrant?~in_data[3:0]:in_data[3:0]}; +reg [15:0] rd_data; + + always @(posedge clock) + if (strobe) + begin + reg_quadrant <= #1 quadrant; + case (rd_addr) + 8'd0 : rd_data <= #1 -16'd12073; + 8'd1 : rd_data <= #1 -16'd12638; + 8'd2 : rd_data <= #1 -16'd11607; + 8'd3 : rd_data <= #1 -16'd12173; + 8'd4 : rd_data <= #1 -16'd10826; + 8'd5 : rd_data <= #1 -16'd11392; + 8'd6 : rd_data <= #1 -16'd10360; + 8'd7 : rd_data <= #1 -16'd10926; + 8'd8 : rd_data <= #1 -16'd18650; + 8'd9 : rd_data <= #1 -16'd19216; + 8'd10 : rd_data <= #1 -16'd18184; + 8'd11 : rd_data <= #1 -16'd18750; + 8'd12 : rd_data <= #1 -16'd17404; + 8'd13 : rd_data <= #1 -16'd17970; + 8'd14 : rd_data <= #1 -16'd16938; + 8'd15 : rd_data <= #1 -16'd17504; + 8'd16 : rd_data <= #1 -16'd10056; + 8'd17 : rd_data <= #1 -16'd10543; + 8'd18 : rd_data <= #1 -16'd9458; + 8'd19 : rd_data <= #1 -16'd9945; + 8'd20 : rd_data <= #1 -16'd9381; + 8'd21 : rd_data <= #1 -16'd9868; + 8'd22 : rd_data <= #1 -16'd8783; + 8'd23 : rd_data <= #1 -16'd9270; + 8'd24 : rd_data <= #1 -16'd15321; + 8'd25 : rd_data <= #1 -16'd15809; + 8'd26 : rd_data <= #1 -16'd14724; + 8'd27 : rd_data <= #1 -16'd15211; + 8'd28 : rd_data <= #1 -16'd14647; + 8'd29 : rd_data <= #1 -16'd15134; + 8'd30 : rd_data <= #1 -16'd14049; + 8'd31 : rd_data <= #1 -16'd14536; + 8'd32 : rd_data <= #1 -16'd8081; + 8'd33 : rd_data <= #1 -16'd8461; + 8'd34 : rd_data <= #1 -16'd7408; + 8'd35 : rd_data <= #1 -16'd7789; + 8'd36 : rd_data <= #1 -16'd7942; + 8'd37 : rd_data <= #1 -16'd8323; + 8'd38 : rd_data <= #1 -16'd7270; + 8'd39 : rd_data <= #1 -16'd7650; + 8'd40 : rd_data <= #1 -16'd11940; + 8'd41 : rd_data <= #1 -16'd12321; + 8'd42 : rd_data <= #1 -16'd11268; + 8'd43 : rd_data <= #1 -16'd11648; + 8'd44 : rd_data <= #1 -16'd11802; + 8'd45 : rd_data <= #1 -16'd12182; + 8'd46 : rd_data <= #1 -16'd11129; + 8'd47 : rd_data <= #1 -16'd11510; + 8'd48 : rd_data <= #1 -16'd6185; + 8'd49 : rd_data <= #1 -16'd6439; + 8'd50 : rd_data <= #1 -16'd5497; + 8'd51 : rd_data <= #1 -16'd5751; + 8'd52 : rd_data <= #1 -16'd6518; + 8'd53 : rd_data <= #1 -16'd6772; + 8'd54 : rd_data <= #1 -16'd5830; + 8'd55 : rd_data <= #1 -16'd6084; + 8'd56 : rd_data <= #1 -16'd8624; + 8'd57 : rd_data <= #1 -16'd8877; + 8'd58 : rd_data <= #1 -16'd7935; + 8'd59 : rd_data <= #1 -16'd8189; + 8'd60 : rd_data <= #1 -16'd8956; + 8'd61 : rd_data <= #1 -16'd9210; + 8'd62 : rd_data <= #1 -16'd8268; + 8'd63 : rd_data <= #1 -16'd8522; + 8'd64 : rd_data <= #1 -16'd4403; + 8'd65 : rd_data <= #1 -16'd4519; + 8'd66 : rd_data <= #1 -16'd3755; + 8'd67 : rd_data <= #1 -16'd3871; + 8'd68 : rd_data <= #1 -16'd5122; + 8'd69 : rd_data <= #1 -16'd5238; + 8'd70 : rd_data <= #1 -16'd4474; + 8'd71 : rd_data <= #1 -16'd4590; + 8'd72 : rd_data <= #1 -16'd5477; + 8'd73 : rd_data <= #1 -16'd5593; + 8'd74 : rd_data <= #1 -16'd4829; + 8'd75 : rd_data <= #1 -16'd4945; + 8'd76 : rd_data <= #1 -16'd6196; + 8'd77 : rd_data <= #1 -16'd6312; + 8'd78 : rd_data <= #1 -16'd5548; + 8'd79 : rd_data <= #1 -16'd5664; + 8'd80 : rd_data <= #1 -16'd2765; + 8'd81 : rd_data <= #1 -16'd2741; + 8'd82 : rd_data <= #1 -16'd2206; + 8'd83 : rd_data <= #1 -16'd2182; + 8'd84 : rd_data <= #1 -16'd3771; + 8'd85 : rd_data <= #1 -16'd3747; + 8'd86 : rd_data <= #1 -16'd3212; + 8'd87 : rd_data <= #1 -16'd3188; + 8'd88 : rd_data <= #1 -16'd2593; + 8'd89 : rd_data <= #1 -16'd2570; + 8'd90 : rd_data <= #1 -16'd2034; + 8'd91 : rd_data <= #1 -16'd2011; + 8'd92 : rd_data <= #1 -16'd3599; + 8'd93 : rd_data <= #1 -16'd3575; + 8'd94 : rd_data <= #1 -16'd3040; + 8'd95 : rd_data <= #1 -16'd3016; + 8'd96 : rd_data <= #1 -16'd1296; + 8'd97 : rd_data <= #1 -16'd1141; + 8'd98 : rd_data <= #1 -16'd866; + 8'd99 : rd_data <= #1 -16'd711; + 8'd100 : rd_data <= #1 -16'd2483; + 8'd101 : rd_data <= #1 -16'd2327; + 8'd102 : rd_data <= #1 -16'd2053; + 8'd103 : rd_data <= #1 -16'd1897; + 8'd104 : rd_data <= #1 -16'd46; + 8'd105 : rd_data <= #1 16'd110; + 8'd106 : rd_data <= #1 16'd384; + 8'd107 : rd_data <= #1 16'd540; + 8'd108 : rd_data <= #1 -16'd1232; + 8'd109 : rd_data <= #1 -16'd1077; + 8'd110 : rd_data <= #1 -16'd802; + 8'd111 : rd_data <= #1 -16'd647; + 8'd112 : rd_data <= #1 -16'd17; + 8'd113 : rd_data <= #1 16'd254; + 8'd114 : rd_data <= #1 16'd255; + 8'd115 : rd_data <= #1 16'd527; + 8'd116 : rd_data <= #1 -16'd1279; + 8'd117 : rd_data <= #1 -16'd1008; + 8'd118 : rd_data <= #1 -16'd1007; + 8'd119 : rd_data <= #1 -16'd735; + 8'd120 : rd_data <= #1 16'd2110; + 8'd121 : rd_data <= #1 16'd2381; + 8'd122 : rd_data <= #1 16'd2382; + 8'd123 : rd_data <= #1 16'd2654; + 8'd124 : rd_data <= #1 16'd848; + 8'd125 : rd_data <= #1 16'd1119; + 8'd126 : rd_data <= #1 16'd1120; + 8'd127 : rd_data <= #1 16'd1392; + 8'd128 : rd_data <= #1 16'd1058; + 8'd129 : rd_data <= #1 16'd1423; + 8'd130 : rd_data <= #1 16'd1157; + 8'd131 : rd_data <= #1 16'd1522; + 8'd132 : rd_data <= #1 -16'd181; + 8'd133 : rd_data <= #1 16'd184; + 8'd134 : rd_data <= #1 -16'd81; + 8'd135 : rd_data <= #1 16'd284; + 8'd136 : rd_data <= #1 16'd3838; + 8'd137 : rd_data <= #1 16'd4203; + 8'd138 : rd_data <= #1 16'd3937; + 8'd139 : rd_data <= #1 16'd4302; + 8'd140 : rd_data <= #1 16'd2599; + 8'd141 : rd_data <= #1 16'd2964; + 8'd142 : rd_data <= #1 16'd2698; + 8'd143 : rd_data <= #1 16'd3063; + 8'd144 : rd_data <= #1 16'd1921; + 8'd145 : rd_data <= #1 16'd2353; + 8'd146 : rd_data <= #1 16'd1845; + 8'd147 : rd_data <= #1 16'd2277; + 8'd148 : rd_data <= #1 16'd792; + 8'd149 : rd_data <= #1 16'd1223; + 8'd150 : rd_data <= #1 16'd716; + 8'd151 : rd_data <= #1 16'd1147; + 8'd152 : rd_data <= #1 16'd5122; + 8'd153 : rd_data <= #1 16'd5553; + 8'd154 : rd_data <= #1 16'd5046; + 8'd155 : rd_data <= #1 16'd5477; + 8'd156 : rd_data <= #1 16'd3993; + 8'd157 : rd_data <= #1 16'd4424; + 8'd158 : rd_data <= #1 16'd3917; + 8'd159 : rd_data <= #1 16'd4348; + 8'd160 : rd_data <= #1 16'd2572; + 8'd161 : rd_data <= #1 16'd3039; + 8'd162 : rd_data <= #1 16'd2330; + 8'd163 : rd_data <= #1 16'd2797; + 8'd164 : rd_data <= #1 16'd1621; + 8'd165 : rd_data <= #1 16'd2088; + 8'd166 : rd_data <= #1 16'd1379; + 8'd167 : rd_data <= #1 16'd1847; + 8'd168 : rd_data <= #1 16'd5967; + 8'd169 : rd_data <= #1 16'd6434; + 8'd170 : rd_data <= #1 16'd5726; + 8'd171 : rd_data <= #1 16'd6193; + 8'd172 : rd_data <= #1 16'd5016; + 8'd173 : rd_data <= #1 16'd5484; + 8'd174 : rd_data <= #1 16'd4775; + 8'd175 : rd_data <= #1 16'd5242; + 8'd176 : rd_data <= #1 16'd3014; + 8'd177 : rd_data <= #1 16'd3486; + 8'd178 : rd_data <= #1 16'd2628; + 8'd179 : rd_data <= #1 16'd3100; + 8'd180 : rd_data <= #1 16'd2291; + 8'd181 : rd_data <= #1 16'd2764; + 8'd182 : rd_data <= #1 16'd1906; + 8'd183 : rd_data <= #1 16'd2378; + 8'd184 : rd_data <= #1 16'd6394; + 8'd185 : rd_data <= #1 16'd6866; + 8'd186 : rd_data <= #1 16'd6008; + 8'd187 : rd_data <= #1 16'd6480; + 8'd188 : rd_data <= #1 16'd5671; + 8'd189 : rd_data <= #1 16'd6144; + 8'd190 : rd_data <= #1 16'd5286; + 8'd191 : rd_data <= #1 16'd5758; + 8'd192 : rd_data <= #1 16'd3258; + 8'd193 : rd_data <= #1 16'd3706; + 8'd194 : rd_data <= #1 16'd2759; + 8'd195 : rd_data <= #1 16'd3206; + 8'd196 : rd_data <= #1 16'd2794; + 8'd197 : rd_data <= #1 16'd3241; + 8'd198 : rd_data <= #1 16'd2294; + 8'd199 : rd_data <= #1 16'd2741; + 8'd200 : rd_data <= #1 16'd6438; + 8'd201 : rd_data <= #1 16'd6886; + 8'd202 : rd_data <= #1 16'd5939; + 8'd203 : rd_data <= #1 16'd6386; + 8'd204 : rd_data <= #1 16'd5974; + 8'd205 : rd_data <= #1 16'd6421; + 8'd206 : rd_data <= #1 16'd5474; + 8'd207 : rd_data <= #1 16'd5921; + 8'd208 : rd_data <= #1 16'd3322; + 8'd209 : rd_data <= #1 16'd3718; + 8'd210 : rd_data <= #1 16'd2745; + 8'd211 : rd_data <= #1 16'd3140; + 8'd212 : rd_data <= #1 16'd3123; + 8'd213 : rd_data <= #1 16'd3519; + 8'd214 : rd_data <= #1 16'd2546; + 8'd215 : rd_data <= #1 16'd2942; + 8'd216 : rd_data <= #1 16'd6150; + 8'd217 : rd_data <= #1 16'd6546; + 8'd218 : rd_data <= #1 16'd5573; + 8'd219 : rd_data <= #1 16'd5969; + 8'd220 : rd_data <= #1 16'd5951; + 8'd221 : rd_data <= #1 16'd6347; + 8'd222 : rd_data <= #1 16'd5374; + 8'd223 : rd_data <= #1 16'd5770; + 8'd224 : rd_data <= #1 16'd3225; + 8'd225 : rd_data <= #1 16'd3547; + 8'd226 : rd_data <= #1 16'd2611; + 8'd227 : rd_data <= #1 16'd2933; + 8'd228 : rd_data <= #1 16'd3281; + 8'd229 : rd_data <= #1 16'd3603; + 8'd230 : rd_data <= #1 16'd2667; + 8'd231 : rd_data <= #1 16'd2989; + 8'd232 : rd_data <= #1 16'd5587; + 8'd233 : rd_data <= #1 16'd5909; + 8'd234 : rd_data <= #1 16'd4973; + 8'd235 : rd_data <= #1 16'd5295; + 8'd236 : rd_data <= #1 16'd5643; + 8'd237 : rd_data <= #1 16'd5965; + 8'd238 : rd_data <= #1 16'd5029; + 8'd239 : rd_data <= #1 16'd5351; + 8'd240 : rd_data <= #1 16'd2992; + 8'd241 : rd_data <= #1 16'd3224; + 8'd242 : rd_data <= #1 16'd2382; + 8'd243 : rd_data <= #1 16'd2615; + 8'd244 : rd_data <= #1 16'd3274; + 8'd245 : rd_data <= #1 16'd3506; + 8'd246 : rd_data <= #1 16'd2664; + 8'd247 : rd_data <= #1 16'd2896; + 8'd248 : rd_data <= #1 16'd4813; + 8'd249 : rd_data <= #1 16'd5046; + 8'd250 : rd_data <= #1 16'd4204; + 8'd251 : rd_data <= #1 16'd4436; + 8'd252 : rd_data <= #1 16'd5095; + 8'd253 : rd_data <= #1 16'd5328; + 8'd254 : rd_data <= #1 16'd4486; + 8'd255 : rd_data <= #1 16'd4718; + endcase // case(rd_addr) + end //if (strobe) + assign out_data[15:0]=reg_quadrant?-rd_data:rd_data; + sign_extend #(16,18) + ext_output (.in(out_data),.out(ext_out_data)); + +endmodule // rrc_coeff_ram_generated_0 + +//bw= 16 data_size= 5 abs_max= 32767 len= 16 +module rrc_coeff_ram_generated1_1 (input clock, input strobe, input [3:0] phase, input [4:0] in_data, output [15:0] out_data,output [17:0] ext_out_data); + +reg reg_quadrant; +wire quadrant=in_data[4]; +wire [7:0] rd_addr={phase,quadrant?~in_data[3:0]:in_data[3:0]}; +reg [15:0] rd_data; + + always @(posedge clock) + if (strobe) + begin + reg_quadrant <= #1 quadrant; + case (rd_addr) + 8'd0 : rd_data <= #1 -16'd12073; + 8'd1 : rd_data <= #1 16'd17504; + 8'd2 : rd_data <= #1 -16'd18650; + 8'd3 : rd_data <= #1 16'd10926; + 8'd4 : rd_data <= #1 -16'd10826; + 8'd5 : rd_data <= #1 16'd18750; + 8'd6 : rd_data <= #1 -16'd17404; + 8'd7 : rd_data <= #1 16'd12173; + 8'd8 : rd_data <= #1 -16'd11607; + 8'd9 : rd_data <= #1 16'd17970; + 8'd10 : rd_data <= #1 -16'd18184; + 8'd11 : rd_data <= #1 16'd11392; + 8'd12 : rd_data <= #1 -16'd10360; + 8'd13 : rd_data <= #1 16'd19216; + 8'd14 : rd_data <= #1 -16'd16938; + 8'd15 : rd_data <= #1 16'd12638; + 8'd16 : rd_data <= #1 -16'd14094; + 8'd17 : rd_data <= #1 16'd20310; + 8'd18 : rd_data <= #1 -16'd21804; + 8'd19 : rd_data <= #1 16'd12600; + 8'd20 : rd_data <= #1 -16'd12273; + 8'd21 : rd_data <= #1 16'd22132; + 8'd22 : rd_data <= #1 -16'd19982; + 8'd23 : rd_data <= #1 16'd14422; + 8'd24 : rd_data <= #1 -16'd13812; + 8'd25 : rd_data <= #1 16'd20592; + 8'd26 : rd_data <= #1 -16'd21522; + 8'd27 : rd_data <= #1 16'd12882; + 8'd28 : rd_data <= #1 -16'd11991; + 8'd29 : rd_data <= #1 16'd22413; + 8'd30 : rd_data <= #1 -16'd19700; + 8'd31 : rd_data <= #1 16'd14704; + 8'd32 : rd_data <= #1 -16'd16081; + 8'd33 : rd_data <= #1 16'd22854; + 8'd34 : rd_data <= #1 -16'd24657; + 8'd35 : rd_data <= #1 16'd14278; + 8'd36 : rd_data <= #1 -16'd13719; + 8'd37 : rd_data <= #1 16'd25216; + 8'd38 : rd_data <= #1 -16'd22295; + 8'd39 : rd_data <= #1 16'd16640; + 8'd40 : rd_data <= #1 -16'd16026; + 8'd41 : rd_data <= #1 16'd22909; + 8'd42 : rd_data <= #1 -16'd24602; + 8'd43 : rd_data <= #1 16'd14333; + 8'd44 : rd_data <= #1 -16'd13664; + 8'd45 : rd_data <= #1 16'd25271; + 8'd46 : rd_data <= #1 -16'd22240; + 8'd47 : rd_data <= #1 16'd16695; + 8'd48 : rd_data <= #1 -16'd17997; + 8'd49 : rd_data <= #1 16'd25037; + 8'd50 : rd_data <= #1 -16'd27089; + 8'd51 : rd_data <= #1 16'd15945; + 8'd52 : rd_data <= #1 -16'd15169; + 8'd53 : rd_data <= #1 16'd27865; + 8'd54 : rd_data <= #1 -16'd24261; + 8'd55 : rd_data <= #1 16'd18773; + 8'd56 : rd_data <= #1 -16'd18196; + 8'd57 : rd_data <= #1 16'd24838; + 8'd58 : rd_data <= #1 -16'd27288; + 8'd59 : rd_data <= #1 16'd15746; + 8'd60 : rd_data <= #1 -16'd15368; + 8'd61 : rd_data <= #1 16'd27666; + 8'd62 : rd_data <= #1 -16'd24460; + 8'd63 : rd_data <= #1 16'd18574; + 8'd64 : rd_data <= #1 -16'd19806; + 8'd65 : rd_data <= #1 16'd26771; + 8'd66 : rd_data <= #1 -16'd28986; + 8'd67 : rd_data <= #1 16'd17591; + 8'd68 : rd_data <= #1 -16'd16627; + 8'd69 : rd_data <= #1 16'd29951; + 8'd70 : rd_data <= #1 -16'd25806; + 8'd71 : rd_data <= #1 16'd20771; + 8'd72 : rd_data <= #1 -16'd20271; + 8'd73 : rd_data <= #1 16'd26306; + 8'd74 : rd_data <= #1 -16'd29451; + 8'd75 : rd_data <= #1 16'd17126; + 8'd76 : rd_data <= #1 -16'd17091; + 8'd77 : rd_data <= #1 16'd29486; + 8'd78 : rd_data <= #1 -16'd26271; + 8'd79 : rd_data <= #1 16'd20306; + 8'd80 : rd_data <= #1 -16'd21478; + 8'd81 : rd_data <= #1 16'd27977; + 8'd82 : rd_data <= #1 -16'd30249; + 8'd83 : rd_data <= #1 16'd19206; + 8'd84 : rd_data <= #1 -16'd18098; + 8'd85 : rd_data <= #1 16'd31357; + 8'd86 : rd_data <= #1 -16'd26869; + 8'd87 : rd_data <= #1 16'd22586; + 8'd88 : rd_data <= #1 -16'd22200; + 8'd89 : rd_data <= #1 16'd27255; + 8'd90 : rd_data <= #1 -16'd30972; + 8'd91 : rd_data <= #1 16'd18483; + 8'd92 : rd_data <= #1 -16'd18820; + 8'd93 : rd_data <= #1 16'd30635; + 8'd94 : rd_data <= #1 -16'd27592; + 8'd95 : rd_data <= #1 16'd21863; + 8'd96 : rd_data <= #1 -16'd22984; + 8'd97 : rd_data <= #1 16'd28594; + 8'd98 : rd_data <= #1 -16'd30797; + 8'd99 : rd_data <= #1 16'd20781; + 8'd100 : rd_data <= #1 -16'd19588; + 8'd101 : rd_data <= #1 16'd31990; + 8'd102 : rd_data <= #1 -16'd27402; + 8'd103 : rd_data <= #1 16'd24176; + 8'd104 : rd_data <= #1 -16'd23935; + 8'd105 : rd_data <= #1 16'd27643; + 8'd106 : rd_data <= #1 -16'd31748; + 8'd107 : rd_data <= #1 16'd19830; + 8'd108 : rd_data <= #1 -16'd20539; + 8'd109 : rd_data <= #1 16'd31039; + 8'd110 : rd_data <= #1 -16'd28353; + 8'd111 : rd_data <= #1 16'd23225; + 8'd112 : rd_data <= #1 -16'd24303; + 8'd113 : rd_data <= #1 16'd28577; + 8'd114 : rd_data <= #1 -16'd30572; + 8'd115 : rd_data <= #1 16'd22307; + 8'd116 : rd_data <= #1 -16'd21102; + 8'd117 : rd_data <= #1 16'd31777; + 8'd118 : rd_data <= #1 -16'd27371; + 8'd119 : rd_data <= #1 16'd25508; + 8'd120 : rd_data <= #1 -16'd25432; + 8'd121 : rd_data <= #1 16'd27447; + 8'd122 : rd_data <= #1 -16'd31701; + 8'd123 : rd_data <= #1 16'd21178; + 8'd124 : rd_data <= #1 -16'd22231; + 8'd125 : rd_data <= #1 16'd30648; + 8'd126 : rd_data <= #1 -16'd28500; + 8'd127 : rd_data <= #1 16'd24379; + 8'd128 : rd_data <= #1 -16'd25418; + 8'd129 : rd_data <= #1 16'd27899; + 8'd130 : rd_data <= #1 -16'd29540; + 8'd131 : rd_data <= #1 16'd23778; + 8'd132 : rd_data <= #1 -16'd22639; + 8'd133 : rd_data <= #1 16'd30679; + 8'd134 : rd_data <= #1 -16'd26760; + 8'd135 : rd_data <= #1 16'd26557; + 8'd136 : rd_data <= #1 -16'd26657; + 8'd137 : rd_data <= #1 16'd26661; + 8'd138 : rd_data <= #1 -16'd30778; + 8'd139 : rd_data <= #1 16'd22539; + 8'd140 : rd_data <= #1 -16'd23877; + 8'd141 : rd_data <= #1 16'd29440; + 8'd142 : rd_data <= #1 -16'd27999; + 8'd143 : rd_data <= #1 16'd25319; + 8'd144 : rd_data <= #1 -16'd26321; + 8'd145 : rd_data <= #1 16'd26558; + 8'd146 : rd_data <= #1 -16'd27696; + 8'd147 : rd_data <= #1 16'd25183; + 8'd148 : rd_data <= #1 -16'd24194; + 8'd149 : rd_data <= #1 16'd28685; + 8'd150 : rd_data <= #1 -16'd25569; + 8'd151 : rd_data <= #1 16'd27310; + 8'd152 : rd_data <= #1 -16'd27583; + 8'd153 : rd_data <= #1 16'd25296; + 8'd154 : rd_data <= #1 -16'd28957; + 8'd155 : rd_data <= #1 16'd23922; + 8'd156 : rd_data <= #1 -16'd25456; + 8'd157 : rd_data <= #1 16'd27423; + 8'd158 : rd_data <= #1 -16'd26830; + 8'd159 : rd_data <= #1 16'd26049; + 8'd160 : rd_data <= #1 -16'd27007; + 8'd161 : rd_data <= #1 16'd24570; + 8'd162 : rd_data <= #1 -16'd25064; + 8'd163 : rd_data <= #1 16'd26514; + 8'd164 : rd_data <= #1 -16'd25757; + 8'd165 : rd_data <= #1 16'd25821; + 8'd166 : rd_data <= #1 -16'd23814; + 8'd167 : rd_data <= #1 16'd27764; + 8'd168 : rd_data <= #1 -16'd28194; + 8'd169 : rd_data <= #1 16'd23384; + 8'd170 : rd_data <= #1 -16'd26251; + 8'd171 : rd_data <= #1 16'd25327; + 8'd172 : rd_data <= #1 -16'd26943; + 8'd173 : rd_data <= #1 16'd24634; + 8'd174 : rd_data <= #1 -16'd25000; + 8'd175 : rd_data <= #1 16'd26578; + 8'd176 : rd_data <= #1 -16'd27481; + 8'd177 : rd_data <= #1 16'd21974; + 8'd178 : rd_data <= #1 -16'd21699; + 8'd179 : rd_data <= #1 16'd27756; + 8'd180 : rd_data <= #1 -16'd27309; + 8'd181 : rd_data <= #1 16'd22146; + 8'd182 : rd_data <= #1 -16'd21528; + 8'd183 : rd_data <= #1 16'd27927; + 8'd184 : rd_data <= #1 -16'd28486; + 8'd185 : rd_data <= #1 16'd20969; + 8'd186 : rd_data <= #1 -16'd22705; + 8'd187 : rd_data <= #1 16'd26750; + 8'd188 : rd_data <= #1 -16'd28315; + 8'd189 : rd_data <= #1 16'd21140; + 8'd190 : rd_data <= #1 -16'd22533; + 8'd191 : rd_data <= #1 16'd26922; + 8'd192 : rd_data <= #1 -16'd27750; + 8'd193 : rd_data <= #1 16'd18827; + 8'd194 : rd_data <= #1 -16'd17683; + 8'd195 : rd_data <= #1 16'd28895; + 8'd196 : rd_data <= #1 -16'd28824; + 8'd197 : rd_data <= #1 16'd17753; + 8'd198 : rd_data <= #1 -16'd18757; + 8'd199 : rd_data <= #1 16'd27820; + 8'd200 : rd_data <= #1 -16'd28469; + 8'd201 : rd_data <= #1 16'd18108; + 8'd202 : rd_data <= #1 -16'd18402; + 8'd203 : rd_data <= #1 16'd28176; + 8'd204 : rd_data <= #1 -16'd29543; + 8'd205 : rd_data <= #1 16'd17034; + 8'd206 : rd_data <= #1 -16'd19476; + 8'd207 : rd_data <= #1 16'd27101; + 8'd208 : rd_data <= #1 -16'd27829; + 8'd209 : rd_data <= #1 16'd15205; + 8'd210 : rd_data <= #1 -16'd13122; + 8'd211 : rd_data <= #1 16'd29912; + 8'd212 : rd_data <= #1 -16'd30267; + 8'd213 : rd_data <= #1 16'd12767; + 8'd214 : rd_data <= #1 -16'd15560; + 8'd215 : rd_data <= #1 16'd27474; + 8'd216 : rd_data <= #1 -16'd28162; + 8'd217 : rd_data <= #1 16'd14872; + 8'd218 : rd_data <= #1 -16'd13455; + 8'd219 : rd_data <= #1 16'd29579; + 8'd220 : rd_data <= #1 -16'd30600; + 8'd221 : rd_data <= #1 16'd12434; + 8'd222 : rd_data <= #1 -16'd15893; + 8'd223 : rd_data <= #1 16'd27141; + 8'd224 : rd_data <= #1 -16'd27738; + 8'd225 : rd_data <= #1 16'd11197; + 8'd226 : rd_data <= #1 -16'd8148; + 8'd227 : rd_data <= #1 16'd30787; + 8'd228 : rd_data <= #1 -16'd31598; + 8'd229 : rd_data <= #1 16'd7337; + 8'd230 : rd_data <= #1 -16'd12008; + 8'd231 : rd_data <= #1 16'd26927; + 8'd232 : rd_data <= #1 -16'd27600; + 8'd233 : rd_data <= #1 16'd11335; + 8'd234 : rd_data <= #1 -16'd8009; + 8'd235 : rd_data <= #1 16'd30926; + 8'd236 : rd_data <= #1 -16'd31459; + 8'd237 : rd_data <= #1 16'd7476; + 8'd238 : rd_data <= #1 -16'd11869; + 8'd239 : rd_data <= #1 16'd27066; + 8'd240 : rd_data <= #1 -16'd27501; + 8'd241 : rd_data <= #1 16'd6903; + 8'd242 : rd_data <= #1 -16'd2909; + 8'd243 : rd_data <= #1 16'd31495; + 8'd244 : rd_data <= #1 -16'd32767; + 8'd245 : rd_data <= #1 16'd1637; + 8'd246 : rd_data <= #1 -16'd8175; + 8'd247 : rd_data <= #1 16'd26229; + 8'd248 : rd_data <= #1 -16'd26827; + 8'd249 : rd_data <= #1 16'd7577; + 8'd250 : rd_data <= #1 -16'd2235; + 8'd251 : rd_data <= #1 16'd32169; + 8'd252 : rd_data <= #1 -16'd32093; + 8'd253 : rd_data <= #1 16'd2312; + 8'd254 : rd_data <= #1 -16'd7501; + 8'd255 : rd_data <= #1 16'd26903; + endcase // case(rd_addr) + end //if (strobe) + assign out_data[15:0]=reg_quadrant?-rd_data:rd_data; + sign_extend #(16,18) + ext_output (.in(out_data),.out(ext_out_data)); + +endmodule // rrc_coeff_ram_generated_1 + +//bw= 9 data_size= 1 abs_max= 244 len= 1 +module rrc_coeff_ram_generated1_2 (input clock, input strobe, input [3:0] phase, input [0:0] in_data, output [8:0] out_data,output [17:0] ext_out_data); + +reg reg_quadrant; +wire quadrant=in_data[0]; +wire [3:0] rd_addr=phase; +reg [8:0] rd_data; + + always @(posedge clock) + if (strobe) + begin + reg_quadrant <= #1 quadrant; + case (rd_addr) + 4'd0 : rd_data <= #1 -9'd67; + 4'd1 : rd_data <= #1 -9'd116; + 4'd2 : rd_data <= #1 -9'd161; + 4'd3 : rd_data <= #1 -9'd198; + 4'd4 : rd_data <= #1 -9'd224; + 4'd5 : rd_data <= #1 -9'd236; + 4'd6 : rd_data <= #1 -9'd234; + 4'd7 : rd_data <= #1 -9'd216; + 4'd8 : rd_data <= #1 -9'd183; + 4'd9 : rd_data <= #1 -9'd136; + 4'd10 : rd_data <= #1 -9'd78; + 4'd11 : rd_data <= #1 -9'd12; + 4'd12 : rd_data <= #1 9'd58; + 4'd13 : rd_data <= #1 9'd127; + 4'd14 : rd_data <= #1 9'd190; + 4'd15 : rd_data <= #1 9'd244; + endcase // case(rd_addr) + end //if (strobe) + assign out_data[8:0]=reg_quadrant?-rd_data:rd_data; + sign_extend #(9,18) + ext_output (.in(out_data),.out(ext_out_data)); + +endmodule // rrc_coeff_ram_generated_2 + +//bw_memory [4, 4, 0] data_size 5 +module frac_interp_1 + + (input clock, input reset, input enable, + output reg strobe_in, input strobe_out, + input wire [4:0] tx_shift, + input wire [15:0] signal_in, + output reg [15:0] signal_out); + +reg [3:0] phase;//max 16 phases + +reg [3:0] in_count;//16 bits in every register + +reg [15:0] input_16; + +reg [15:0] shift_16_0; +wire get_bit= (phase==4'd15); + + always @(posedge clock) + if (reset) + begin + strobe_in <= #1 0;// Reset + in_count <=#1 0; + input_16 <= #1 0; + + shift_16_0 <= #1 0; + + end //if (reset) + else //if (reset) + begin + if(enable & strobe_out & get_bit & (in_count == 4'd15)) + strobe_in <=#1 1'd1;//Only works if output of previous stage is registered and only updates on this strobe_in + else // if(strobe_in) //input a new 16 bit word and shift all regs 16 bit to the right= to next register) + strobe_in <= #1 0;//notice the else is always executed, even if there is no strobe_out so strobe_in will only be high for 1 clock + + if (enable & strobe_out) + begin + if ( get_bit) + + begin //shift input 1 bit to the left + if(in_count == 4'd15) //(strobe_in) //if(in_count == 4'd0) + begin + //strobe_in <=#1 1'd1;//Only works if output of previous stage is registered and only updates on this strobe_in + input_16 <= #1 signal_in; + end //if(in_count == 4'd0) + else //if(in_count == 4'd0) + begin + input_16 <= #1 {1'd0,input_16[15:1]};//just shift right //MDVH 14feb2007 + //input_16 <= #1 {input_16[14:0],1'd0};//just shift left //MDVH 14feb2007 + end // if(in_count == 4'd0) else + //shift_16_0 <= #1 {shift_16_0[14:0],input_16[15]};//MDVH 14feb2007 + shift_16_0 <= #1 {input_16[0],shift_16_0[15:1]};//MDVH 14feb2007 + + + in_count <= #1 in_count+4'd1; + end //if ((phase==.... + end //if (enable & strobe_out) + end // if (reset) else + + always @(posedge clock) + if (reset) + phase <=#1 0; + else if (enable & strobe_out) + phase <=#1 phase + 4'd1;//phase will roll-over to zero and start again + + +wire [4:0] data_0; +wire [4:0] data_1; +wire [0:0] data_2; +assign data_2=shift_16_0[10:10]; +assign data_1=shift_16_0[9:5]; +assign data_0=shift_16_0[4:0]; +wire [17:0] sum_0; +wire [17:0] sum_1; +wire [17:0] sum_2; +wire [17:0] sum_3; +assign sum_3=0; +reg [17:0] sum_all; + +//wire [15:0] sum_all_16bit; + + rrc_coeff_ram_generated1_0 rrc_coeff_ram_0 ( .clock(clock),.strobe(strobe_out),.phase(phase),.in_data(data_0),.out_data(),.ext_out_data(sum_0) ); + rrc_coeff_ram_generated1_1 rrc_coeff_ram_1 ( .clock(clock),.strobe(strobe_out),.phase(phase),.in_data(data_1),.out_data(),.ext_out_data(sum_1) ); + rrc_coeff_ram_generated1_2 rrc_coeff_ram_2 ( .clock(clock),.strobe(strobe_out),.phase(phase),.in_data(data_2),.out_data(),.ext_out_data(sum_2) ); +//assign sum_all= sum_0 + sum_1 + sum_2; +reg [17:0] sum_01; +reg [17:0] sum_23; +reg [17:0] sum_0123; + + always @(posedge clock) + if (reset) + begin + + sum_01 <= #1 0; + sum_23 <= #1 0; + sum_0123 <= #1 0; + + sum_all <=#1 0; + signal_out <= #1 0; + end + else if (enable & strobe_out) + begin + + sum_01 <= #1 sum_0+sum_1; + sum_23 <= #1 sum_2+sum_3; + sum_0123 <= #1 sum_01+sum_23; + sum_all <= #1 sum_0123; + + case(tx_shift) + //5'd0 : signal_out <= #1 round_16(sum_all);//no gain reduce + 5'd0 : signal_out <= #1 { sum_all[16:1] + (sum_all[17] & ( sum_all[0] )) }; + 5'd1 : signal_out <= #1 { sum_all[17:2] + (sum_all[17] & (|sum_all[1:0])) }; + 5'd2 : signal_out <= #1 { {{(1){sum_all[17]}}, sum_all[17:3]} + (sum_all[17] & (|sum_all[2:0])) }; + 5'd3 : signal_out <= #1 { {{(2){sum_all[17]}}, sum_all[17:4]} + (sum_all[17] & (|sum_all[3:0])) }; + 5'd4 : signal_out <= #1 { {{(3){sum_all[17]}}, sum_all[17:5]} + (sum_all[17] & (|sum_all[4:0])) }; + 5'd5 : signal_out <= #1 { {{(4){sum_all[17]}}, sum_all[17:6]} + (sum_all[17] & (|sum_all[5:0])) }; + 5'd6 : signal_out <= #1 { {{(5){sum_all[17]}}, sum_all[17:7]} + (sum_all[17] & (|sum_all[6:0])) }; + 5'd7 : signal_out <= #1 { {{(6){sum_all[17]}}, sum_all[17:8]} + (sum_all[17] & (|sum_all[7:0])) }; + 5'd8 : signal_out <= #1 { {{(7){sum_all[17]}}, sum_all[17:9]} + (sum_all[17] & (|sum_all[8:0])) }; + 5'd9 : signal_out <= #1 { {{(8){sum_all[17]}}, sum_all[17:10]} + (sum_all[17] & (|sum_all[9:0])) }; + 5'd10 : signal_out <= #1 { {{(9){sum_all[17]}},sum_all[17:11]} + (sum_all[17] & (|sum_all[10:0]))}; + 5'd11 : signal_out <= #1 { {{(10){sum_all[17]}},sum_all[17:12]} + (sum_all[17] & (|sum_all[11:0]))}; + 5'd12 : signal_out <= #1 { {{(11){sum_all[17]}},sum_all[17:13]} + (sum_all[17] & (|sum_all[12:0]))}; + 5'd13 : signal_out <= #1 { {{(12){sum_all[17]}},sum_all[17:14]} + (sum_all[17] & (|sum_all[13:0]))}; + 5'd14 : signal_out <= #1 { {{(13){sum_all[17]}},sum_all[17:15]} + (sum_all[17] & (|sum_all[14:0]))}; + 5'd15 : signal_out <= #1 { {{(14){sum_all[17]}},sum_all[17:16]} + (sum_all[17] & (|sum_all[15:0]))}; + + -5'd1 : signal_out <= #1 {sum_all[15:0] }; + -5'd2 : signal_out <= #1 {sum_all[14:0] ,{(1){1'b0}}}; + -5'd3 : signal_out <= #1 {sum_all[13:0] ,{(2){1'b0}}}; + -5'd4 : signal_out <= #1 {sum_all[12:0] ,{(3){1'b0}}}; + -5'd5 : signal_out <= #1 {sum_all[11:0] ,{(4){1'b0}}}; + -5'd6 : signal_out <= #1 {sum_all[10:0] ,{(5){1'b0}}}; + -5'd7 : signal_out <= #1 {sum_all[9:0] ,{(6){1'b0}}}; + -5'd8 : signal_out <= #1 {sum_all[8:0] ,{(7){1'b0}}}; + -5'd9 : signal_out <= #1 {sum_all[7:0] ,{(8){1'b0}}}; + -5'd10 : signal_out <= #1 {sum_all[6:0] ,{(9){1'b0}}}; + -5'd11 : signal_out <= #1 {sum_all[5:0] ,{(10){1'b0}}}; + -5'd12 : signal_out <= #1 {sum_all[4:0] ,{(11){1'b0}}}; + -5'd13 : signal_out <= #1 {sum_all[3:0] ,{(12){1'b0}}}; + -5'd14 : signal_out <= #1 {sum_all[2:0] ,{(13){1'b0}}}; + -5'd15 : signal_out <= #1 {sum_all[1:0] ,{(14){1'b0}}}; + + default : signal_out <= #1 { sum_all[16:1] + (sum_all[17] & ( sum_all[0] )) }; + //signal_out <= #1 { sum_all[17:2] + (sum_all[17] & (|sum_all[1:0])) }; + endcase // case(shift) + + //sum_all_14bit <= #1 sum_0123[16:3] + (sum_0123[16] & |sum_0123[2:0]);//round to 14 bit (reduce gain by 2 bit = 12 dB) + + //signal_out <= #1 round_16(sum_all);//no gain reduce + //signal_out <= #1 {{(2){sum_all_14bit[13]}},sum_all_14bit};//sign_extend to 16 bit (gain reduced by 2 bit = 12 dB) + + end //else if (enable & strobe_out) + + +/*assign sum_all_16bit=round_16(sum_all); +//register the output to ease timing of the DDR DAC output + always @(posedge clock or posedge reset) + if (reset) + signal_out <= #1 0; // Reset + else + signal_out <= #1 sum_all_16bit; +*/ +//round to 16 bit +// function [15:0] round_16; +// input [16:0] in_val; +// round_16 = in_val[16:1] + (in_val[16] & |in_val[0]);//round_16 = in_val[16:1] + (in_val[16] & in_val[0]) +// endfunction // round_16 + + +endmodule //module frac_interp_1 Index: usrp/fpga/sdr_lib/tx_chain_0.v =================================================================== --- usrp/fpga/sdr_lib/tx_chain_0.v (revision 0) +++ usrp/fpga/sdr_lib/tx_chain_0.v (revision 0) @@ -0,0 +1,76 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// Copyright (C) 2006 Martin Dudok van Heel +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +module tx_chain_0 + (input clock, + input reset, + input enable, + input wire [7:0] interp_rate, + input sample_strobe, + output interpolator_strobe, + input wire [31:0] freq, + input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe, + input wire [15:0] i_in, + input wire [15:0] q_in, + output wire [15:0] i_out, + output wire [15:0] q_out + ); + +parameter TX_SHIFT_ADDR = 0; + + wire [15:0] bb_i, bb_q; + wire [4:0] tx_shift; + setting_reg #(65) sr_tx_shift0(.clock(clock),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(tx_shift)); + + //DAC will interpolate by 4 too so for gnuradio interpolation rate must be set to round(interp_ratio*4) + //TODO optional:change the code to set the DAC to interpolate by 2 in stead of 4 (consequence: we loose fine controll for the duc) + frac_interp_0 frac_interp_i + ( .clock(clock),.reset(reset),.enable(enable), + .strobe_in(interpolator_strobe),.strobe_out(sample_strobe), + .tx_shift(tx_shift), + .signal_in(i_in),.signal_out(bb_i) ); + + frac_interp_0 frac_interp_q + ( .clock(clock),.reset(reset),.enable(enable), + .strobe_in(),.strobe_out(sample_strobe), + .tx_shift(tx_shift), + .signal_in(q_in),.signal_out(bb_q) ); + + +`define NOCORDIC_TX +`ifdef NOCORDIC_TX + assign i_out = bb_i; + assign q_out = bb_q; +`else + wire [31:0] phase; + + phase_acc phase_acc_tx + (.clk(clock),.reset(reset),.enable(enable), + .strobe(sample_strobe),.freq(freq),.phase(phase) ); + + cordic tx_cordic_0 + ( .clock(clock),.reset(reset),.enable(sample_strobe), + .xi(bb_i),.yi(bb_q),.zi(phase[31:16]), + .xo(i_out),.yo(q_out),.zo() ); +`endif + +endmodule // tx_chain Index: usrp/fpga/sdr_lib/tx_chain_1.v =================================================================== --- usrp/fpga/sdr_lib/tx_chain_1.v (revision 0) +++ usrp/fpga/sdr_lib/tx_chain_1.v (revision 0) @@ -0,0 +1,67 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// Copyright (C) 2006 Martin Dudok van Heel +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +module tx_chain_1 + (input clock, + input reset, + input enable, + input wire [7:0] interp_rate, + input sample_strobe, + output interpolator_strobe, + input wire [31:0] freq, + input wire [15:0] i_in, + input wire [15:0] q_in, + output wire [15:0] i_out, + output wire [15:0] q_out + ); + + wire [15:0] bb_i, bb_q; + //DAC will interpolate by 4 too so for gnuradio interpolation rate must be set to round(interp_ratio*4) + //TODO optional:change the code to set the DAC to interpolate by 2 in stead of 4 (consequence: we loose fine controll for the duc) + frac_interp_1 frac_interp_i + ( .clock(clock),.reset(reset),.enable(enable), + .strobe_in(interpolator_strobe),.strobe_out(sample_strobe), + .signal_in(i_in),.signal_out(bb_i) ); + + frac_interp_1 frac_interp_q + ( .clock(clock),.reset(reset),.enable(enable), + .strobe_in(),.strobe_out(sample_strobe), + .signal_in(q_in),.signal_out(bb_q) ); + +`define NOCORDIC_TX +`ifdef NOCORDIC_TX + assign i_out = bb_i; + assign q_out = bb_q; +`else + wire [31:0] phase; + + phase_acc phase_acc_tx + (.clk(clock),.reset(reset),.enable(enable), + .strobe(sample_strobe),.freq(freq),.phase(phase) ); + + cordic tx_cordic_0 + ( .clock(clock),.reset(reset),.enable(sample_strobe), + .xi(bb_i),.yi(bb_q),.zi(phase[31:16]), + .xo(i_out),.yo(q_out),.zo() ); +`endif + +endmodule // tx_chain Index: usrp/fpga/sdr_lib/frac_interp_alpha0.2_int16_dec10_DACint4X_chan0.v =================================================================== --- usrp/fpga/sdr_lib/frac_interp_alpha0.2_int16_dec10_DACint4X_chan0.v (revision 0) +++ usrp/fpga/sdr_lib/frac_interp_alpha0.2_int16_dec10_DACint4X_chan0.v (revision 0) @@ -0,0 +1,879 @@ +// -*- verilog -*- +// +// Polyphase interpolating Root-Raised-Cosine filter +// +// Copyright (C) 2007 Martin Dudok van Heel +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// +// Polyphase interpolating Root-Raised-Cosine filter +// Interpolation ratio can be fractional (float) +// +// This file was generated by ./generate_frac_interp_05nov2007.py at 2007-11-08 00:15:23.096178 +// Written by Martin Dudok van Heel, 2007 +// Olifantasia +// +// Contact: http://www.olifantasia.com/gnuradio/contact.gif or nldudok1_olifantasia_com +// http://www.olifantasia.com +// +// This file can be used to build a special purpose firmware for the USRP +// USRP = Universal Software Radio Peripheral +// This special purpose firmware in combination with the GnuRadio framework can be used to create a high speed QPSK transmitter +// Depending on the decimation and interpolation factors used, the symbolrate can be from 2 to 20 Msymbols/sec +// The corresponding QPSK bitrate is 4 to 40 Mbit/sec +// alpha= 0.2 +// interpolation = 16.0 decimation= 10.0 interp_ratio= 1.6 decim_ratio= 0.625 +// symbol rate = 20.0 Msymbol/sec +// QPSK bitrate = 40.0 Mbit/sec +// +//fractional ntaps 17.6 +//ntaps_per_filter= 11 +//nfilters= 16 +// s f incr d_mu ii oo step +// 0.0 0.0 0 0.0 0 0 0 +// 0.625 0.0 0 0.625 0 1 1 +// 1.25 1.0 1 0.25 1 2 2 +// 0.875 0.0 0 0.875 1 3 3 +// 1.5 1.0 1 0.5 2 4 4 +// 1.125 1.0 1 0.125 3 5 5 +// 0.75 0.0 0 0.75 3 6 6 +// 1.375 1.0 1 0.375 4 7 7 +// 1.0 1.0 1 0.0 5 8 8 +// 0.625 0.0 0 0.625 5 9 9 +// 1.25 1.0 1 0.25 6 10 10 +// 0.875 0.0 0 0.875 6 11 11 +// 1.5 1.0 1 0.5 7 12 12 +// 1.125 1.0 1 0.125 8 13 13 +// 0.75 0.0 0 0.75 8 14 14 +// 1.375 1.0 1 0.375 9 15 15 +//poly_filter[ 0 ] = +// [-0.016952886801492591, 0.027320014270136073, -0.037678710298681584, 0.04652154604550536, -0.052473019541496996, 1.0531792715130162, -0.052473019541496996, 0.04652154604550536, -0.037678710298681584, 0.027320014270136073, -0.016952886801492591] + +//poly_filter[ 1 ] = +// [0.0064053452259068928, 0.0012467941820681503, -0.019236656305587702, 0.055471404769445419, -0.134652938078933, 0.43836544769923702, 0.79729550875966892, -0.20956911563411504, 0.10265723635479067, -0.052044187277807373, 0.022441577548409291] + +//poly_filter[ 2 ] = +// [-0.011121268801005637, 0.029638149747377985, -0.058136370658318372, 0.10379850880938603, -0.19972149237265682, 0.93418657928447435, 0.25192427285271296, -0.071978363672203727, 0.021231513165556354, -7.7873837828280443e-17, -0.0081946191165304366] + +//poly_filter[ 3 ] = +// [0.0098336035607602488, -0.014526954900680811, 0.016352547900186802, -0.01157728372979675, -0.0082269202043394191, 0.083792247178060913, 1.0226126363290351, -0.1480767079436732, 0.085077499291207725, -0.053624731253201059, 0.031699112977245862] + +//poly_filter[ 4 ] = +// [0.0012862557726307691, 0.012187354345710392, -0.037881534084307146, 0.08476443400746296, -0.18447589163766012, 0.62623488448318076, 0.62623488448318076, -0.18447589163766012, 0.08476443400746296, -0.037881534084307146, 0.012187354345710392] + +//poly_filter[ 5 ] = +// [-0.015543521630860075, 0.031699112977245862, -0.053624731253201059, 0.085077499291207725, -0.1480767079436732, 1.0226126363290351, 0.083792247178060913, -0.0082269202043394191, -0.01157728372979675, 0.016352547900186802, -0.014526954900680811] + +//poly_filter[ 6 ] = +// [0.0093884822181135134, -0.0081946191165304366, -7.7873837828280443e-17, 0.021231513165556354, -0.071978363672203727, 0.25192427285271296, 0.93418657928447435, -0.19972149237265682, 0.10379850880938603, -0.058136370658318372, 0.029638149747377985] + +//poly_filter[ 7 ] = +// [-0.0050099408373175149, 0.022441577548409291, -0.052044187277807373, 0.10265723635479067, -0.20956911563411504, 0.79729550875966892, 0.43836544769923702, -0.134652938078933, 0.055471404769445419, -0.019236656305587702, 0.0012467941820681503] + +//poly_filter[ 8 ] = +// [-0.016952886801492591, 0.027320014270136073, -0.037678710298681584, 0.04652154604550536, -0.052473019541496996, 1.0531792715130162, -0.052473019541496996, 0.04652154604550536, -0.037678710298681584, 0.027320014270136073, -0.016952886801492591] + +//poly_filter[ 9 ] = +// [0.0064053452259068928, 0.0012467941820681503, -0.019236656305587702, 0.055471404769445419, -0.134652938078933, 0.43836544769923702, 0.79729550875966892, -0.20956911563411504, 0.10265723635479067, -0.052044187277807373, 0.022441577548409291] + +//poly_filter[ 10 ] = +// [-0.011121268801005637, 0.029638149747377985, -0.058136370658318372, 0.10379850880938603, -0.19972149237265682, 0.93418657928447435, 0.25192427285271296, -0.071978363672203727, 0.021231513165556354, -7.7873837828280443e-17, -0.0081946191165304366] + +//poly_filter[ 11 ] = +// [0.0098336035607602488, -0.014526954900680811, 0.016352547900186802, -0.01157728372979675, -0.0082269202043394191, 0.083792247178060913, 1.0226126363290351, -0.1480767079436732, 0.085077499291207725, -0.053624731253201059, 0.031699112977245862] + +//poly_filter[ 12 ] = +// [0.0012862557726307691, 0.012187354345710392, -0.037881534084307146, 0.08476443400746296, -0.18447589163766012, 0.62623488448318076, 0.62623488448318076, -0.18447589163766012, 0.08476443400746296, -0.037881534084307146, 0.012187354345710392] + +//poly_filter[ 13 ] = +// [-0.015543521630860075, 0.031699112977245862, -0.053624731253201059, 0.085077499291207725, -0.1480767079436732, 1.0226126363290351, 0.083792247178060913, -0.0082269202043394191, -0.01157728372979675, 0.016352547900186802, -0.014526954900680811] + +//poly_filter[ 14 ] = +// [0.0093884822181135134, -0.0081946191165304366, -7.7873837828280443e-17, 0.021231513165556354, -0.071978363672203727, 0.25192427285271296, 0.93418657928447435, -0.19972149237265682, 0.10379850880938603, -0.058136370658318372, 0.029638149747377985] + +//poly_filter[ 15 ] = +// [-0.0050099408373175149, 0.022441577548409291, -0.052044187277807373, 0.10265723635479067, -0.20956911563411504, 0.79729550875966892, 0.43836544769923702, -0.134652938078933, 0.055471404769445419, -0.019236656305587702, 0.0012467941820681503] + +// total_ntaps= 176 +// ntaps_per_filter= 11 +// nfilters= 16 +// filter resolution= 16 bits +// +//data_size= 5 phase_size= 4 +//abs_max= 1.59993149573 abs_max_16bit= 32767 signed_max_16bit= 32767 signed_min_16bit= -30635 +//nmemories= 3 +//incr_list = [1, 3, 4, 6, 7, 9, 11, 12, 14, 15] +//bw= 15 data_size= 5 abs_max= 8242 len= 16 +module rrc_coeff_ram_generated0_0 (input clock, input strobe, input [3:0] phase, input [4:0] in_data, output [14:0] out_data,output [17:0] ext_out_data); + +reg reg_quadrant; +wire quadrant=in_data[4]; +wire [7:0] rd_addr={phase,quadrant?~in_data[3:0]:in_data[3:0]}; +reg [14:0] rd_data; + + always @(posedge clock) + if (strobe) + begin + reg_quadrant <= #1 quadrant; + case (rd_addr) + 8'd0 : rd_data <= #1 15'd681; + 8'd1 : rd_data <= #1 -15'd13; + 8'd2 : rd_data <= #1 15'd1800; + 8'd3 : rd_data <= #1 15'd1106; + 8'd4 : rd_data <= #1 -15'd862; + 8'd5 : rd_data <= #1 -15'd1557; + 8'd6 : rd_data <= #1 15'd257; + 8'd7 : rd_data <= #1 -15'd437; + 8'd8 : rd_data <= #1 15'd2587; + 8'd9 : rd_data <= #1 15'd1892; + 8'd10 : rd_data <= #1 15'd3706; + 8'd11 : rd_data <= #1 15'd3011; + 8'd12 : rd_data <= #1 15'd1043; + 8'd13 : rd_data <= #1 15'd349; + 8'd14 : rd_data <= #1 15'd2162; + 8'd15 : rd_data <= #1 15'd1468; + 8'd16 : rd_data <= #1 15'd1859; + 8'd17 : rd_data <= #1 15'd2121; + 8'd18 : rd_data <= #1 15'd1910; + 8'd19 : rd_data <= #1 15'd2172; + 8'd20 : rd_data <= #1 15'd1071; + 8'd21 : rd_data <= #1 15'd1333; + 8'd22 : rd_data <= #1 15'd1122; + 8'd23 : rd_data <= #1 15'd1384; + 8'd24 : rd_data <= #1 15'd4131; + 8'd25 : rd_data <= #1 15'd4393; + 8'd26 : rd_data <= #1 15'd4182; + 8'd27 : rd_data <= #1 15'd4444; + 8'd28 : rd_data <= #1 15'd3343; + 8'd29 : rd_data <= #1 15'd3605; + 8'd30 : rd_data <= #1 15'd3394; + 8'd31 : rd_data <= #1 15'd3657; + 8'd32 : rd_data <= #1 15'd2776; + 8'd33 : rd_data <= #1 15'd2320; + 8'd34 : rd_data <= #1 15'd3990; + 8'd35 : rd_data <= #1 15'd3534; + 8'd36 : rd_data <= #1 15'd395; + 8'd37 : rd_data <= #1 -15'd61; + 8'd38 : rd_data <= #1 15'd1609; + 8'd39 : rd_data <= #1 15'd1153; + 8'd40 : rd_data <= #1 15'd7028; + 8'd41 : rd_data <= #1 15'd6572; + 8'd42 : rd_data <= #1 15'd8242; + 8'd43 : rd_data <= #1 15'd7786; + 8'd44 : rd_data <= #1 15'd4646; + 8'd45 : rd_data <= #1 15'd4191; + 8'd46 : rd_data <= #1 15'd5860; + 8'd47 : rd_data <= #1 15'd5405; + 8'd48 : rd_data <= #1 15'd167; + 8'd49 : rd_data <= #1 15'd570; + 8'd50 : rd_data <= #1 -15'd428; + 8'd51 : rd_data <= #1 -15'd25; + 8'd52 : rd_data <= #1 15'd837; + 8'd53 : rd_data <= #1 15'd1239; + 8'd54 : rd_data <= #1 15'd242; + 8'd55 : rd_data <= #1 15'd644; + 8'd56 : rd_data <= #1 -15'd307; + 8'd57 : rd_data <= #1 15'd95; + 8'd58 : rd_data <= #1 -15'd902; + 8'd59 : rd_data <= #1 -15'd500; + 8'd60 : rd_data <= #1 15'd362; + 8'd61 : rd_data <= #1 15'd765; + 8'd62 : rd_data <= #1 -15'd233; + 8'd63 : rd_data <= #1 15'd170; + 8'd64 : rd_data <= #1 15'd2542; + 8'd65 : rd_data <= #1 15'd2595; + 8'd66 : rd_data <= #1 15'd3041; + 8'd67 : rd_data <= #1 15'd3094; + 8'd68 : rd_data <= #1 15'd990; + 8'd69 : rd_data <= #1 15'd1043; + 8'd70 : rd_data <= #1 15'd1490; + 8'd71 : rd_data <= #1 15'd1542; + 8'd72 : rd_data <= #1 15'd6014; + 8'd73 : rd_data <= #1 15'd6067; + 8'd74 : rd_data <= #1 15'd6513; + 8'd75 : rd_data <= #1 15'd6566; + 8'd76 : rd_data <= #1 15'd4462; + 8'd77 : rd_data <= #1 15'd4515; + 8'd78 : rd_data <= #1 15'd4962; + 8'd79 : rd_data <= #1 15'd5014; + 8'd80 : rd_data <= #1 15'd2058; + 8'd81 : rd_data <= #1 15'd1421; + 8'd82 : rd_data <= #1 15'd3356; + 8'd83 : rd_data <= #1 15'd2719; + 8'd84 : rd_data <= #1 -15'd139; + 8'd85 : rd_data <= #1 -15'd776; + 8'd86 : rd_data <= #1 15'd1160; + 8'd87 : rd_data <= #1 15'd523; + 8'd88 : rd_data <= #1 15'd5542; + 8'd89 : rd_data <= #1 15'd4906; + 8'd90 : rd_data <= #1 15'd6841; + 8'd91 : rd_data <= #1 15'd6204; + 8'd92 : rd_data <= #1 15'd3346; + 8'd93 : rd_data <= #1 15'd2709; + 8'd94 : rd_data <= #1 15'd4644; + 8'd95 : rd_data <= #1 15'd4008; + 8'd96 : rd_data <= #1 15'd1015; + 8'd97 : rd_data <= #1 15'd1399; + 8'd98 : rd_data <= #1 15'd679; + 8'd99 : rd_data <= #1 15'd1064; + 8'd100 : rd_data <= #1 15'd1015; + 8'd101 : rd_data <= #1 15'd1399; + 8'd102 : rd_data <= #1 15'd679; + 8'd103 : rd_data <= #1 15'd1064; + 8'd104 : rd_data <= #1 15'd1885; + 8'd105 : rd_data <= #1 15'd2269; + 8'd106 : rd_data <= #1 15'd1549; + 8'd107 : rd_data <= #1 15'd1933; + 8'd108 : rd_data <= #1 15'd1885; + 8'd109 : rd_data <= #1 15'd2269; + 8'd110 : rd_data <= #1 15'd1549; + 8'd111 : rd_data <= #1 15'd1933; + 8'd112 : rd_data <= #1 15'd2898; + 8'd113 : rd_data <= #1 15'd2693; + 8'd114 : rd_data <= #1 15'd3818; + 8'd115 : rd_data <= #1 15'd3612; + 8'd116 : rd_data <= #1 15'd767; + 8'd117 : rd_data <= #1 15'd561; + 8'd118 : rd_data <= #1 15'd1686; + 8'd119 : rd_data <= #1 15'd1481; + 8'd120 : rd_data <= #1 15'd7103; + 8'd121 : rd_data <= #1 15'd6898; + 8'd122 : rd_data <= #1 15'd8023; + 8'd123 : rd_data <= #1 15'd7817; + 8'd124 : rd_data <= #1 15'd4972; + 8'd125 : rd_data <= #1 15'd4766; + 8'd126 : rd_data <= #1 15'd5891; + 8'd127 : rd_data <= #1 15'd5686; + 8'd128 : rd_data <= #1 15'd681; + 8'd129 : rd_data <= #1 -15'd13; + 8'd130 : rd_data <= #1 15'd1800; + 8'd131 : rd_data <= #1 15'd1106; + 8'd132 : rd_data <= #1 -15'd862; + 8'd133 : rd_data <= #1 -15'd1557; + 8'd134 : rd_data <= #1 15'd257; + 8'd135 : rd_data <= #1 -15'd437; + 8'd136 : rd_data <= #1 15'd2587; + 8'd137 : rd_data <= #1 15'd1892; + 8'd138 : rd_data <= #1 15'd3706; + 8'd139 : rd_data <= #1 15'd3011; + 8'd140 : rd_data <= #1 15'd1043; + 8'd141 : rd_data <= #1 15'd349; + 8'd142 : rd_data <= #1 15'd2162; + 8'd143 : rd_data <= #1 15'd1468; + 8'd144 : rd_data <= #1 15'd1859; + 8'd145 : rd_data <= #1 15'd2121; + 8'd146 : rd_data <= #1 15'd1910; + 8'd147 : rd_data <= #1 15'd2172; + 8'd148 : rd_data <= #1 15'd1071; + 8'd149 : rd_data <= #1 15'd1333; + 8'd150 : rd_data <= #1 15'd1122; + 8'd151 : rd_data <= #1 15'd1384; + 8'd152 : rd_data <= #1 15'd4131; + 8'd153 : rd_data <= #1 15'd4393; + 8'd154 : rd_data <= #1 15'd4182; + 8'd155 : rd_data <= #1 15'd4444; + 8'd156 : rd_data <= #1 15'd3343; + 8'd157 : rd_data <= #1 15'd3605; + 8'd158 : rd_data <= #1 15'd3394; + 8'd159 : rd_data <= #1 15'd3657; + 8'd160 : rd_data <= #1 15'd2776; + 8'd161 : rd_data <= #1 15'd2320; + 8'd162 : rd_data <= #1 15'd3990; + 8'd163 : rd_data <= #1 15'd3534; + 8'd164 : rd_data <= #1 15'd395; + 8'd165 : rd_data <= #1 -15'd61; + 8'd166 : rd_data <= #1 15'd1609; + 8'd167 : rd_data <= #1 15'd1153; + 8'd168 : rd_data <= #1 15'd7028; + 8'd169 : rd_data <= #1 15'd6572; + 8'd170 : rd_data <= #1 15'd8242; + 8'd171 : rd_data <= #1 15'd7786; + 8'd172 : rd_data <= #1 15'd4646; + 8'd173 : rd_data <= #1 15'd4191; + 8'd174 : rd_data <= #1 15'd5860; + 8'd175 : rd_data <= #1 15'd5405; + 8'd176 : rd_data <= #1 15'd167; + 8'd177 : rd_data <= #1 15'd570; + 8'd178 : rd_data <= #1 -15'd428; + 8'd179 : rd_data <= #1 -15'd25; + 8'd180 : rd_data <= #1 15'd837; + 8'd181 : rd_data <= #1 15'd1239; + 8'd182 : rd_data <= #1 15'd242; + 8'd183 : rd_data <= #1 15'd644; + 8'd184 : rd_data <= #1 -15'd307; + 8'd185 : rd_data <= #1 15'd95; + 8'd186 : rd_data <= #1 -15'd902; + 8'd187 : rd_data <= #1 -15'd500; + 8'd188 : rd_data <= #1 15'd362; + 8'd189 : rd_data <= #1 15'd765; + 8'd190 : rd_data <= #1 -15'd233; + 8'd191 : rd_data <= #1 15'd170; + 8'd192 : rd_data <= #1 15'd2542; + 8'd193 : rd_data <= #1 15'd2595; + 8'd194 : rd_data <= #1 15'd3041; + 8'd195 : rd_data <= #1 15'd3094; + 8'd196 : rd_data <= #1 15'd990; + 8'd197 : rd_data <= #1 15'd1043; + 8'd198 : rd_data <= #1 15'd1490; + 8'd199 : rd_data <= #1 15'd1542; + 8'd200 : rd_data <= #1 15'd6014; + 8'd201 : rd_data <= #1 15'd6067; + 8'd202 : rd_data <= #1 15'd6513; + 8'd203 : rd_data <= #1 15'd6566; + 8'd204 : rd_data <= #1 15'd4462; + 8'd205 : rd_data <= #1 15'd4515; + 8'd206 : rd_data <= #1 15'd4962; + 8'd207 : rd_data <= #1 15'd5014; + 8'd208 : rd_data <= #1 15'd2058; + 8'd209 : rd_data <= #1 15'd1421; + 8'd210 : rd_data <= #1 15'd3356; + 8'd211 : rd_data <= #1 15'd2719; + 8'd212 : rd_data <= #1 -15'd139; + 8'd213 : rd_data <= #1 -15'd776; + 8'd214 : rd_data <= #1 15'd1160; + 8'd215 : rd_data <= #1 15'd523; + 8'd216 : rd_data <= #1 15'd5542; + 8'd217 : rd_data <= #1 15'd4906; + 8'd218 : rd_data <= #1 15'd6841; + 8'd219 : rd_data <= #1 15'd6204; + 8'd220 : rd_data <= #1 15'd3346; + 8'd221 : rd_data <= #1 15'd2709; + 8'd222 : rd_data <= #1 15'd4644; + 8'd223 : rd_data <= #1 15'd4008; + 8'd224 : rd_data <= #1 15'd1015; + 8'd225 : rd_data <= #1 15'd1399; + 8'd226 : rd_data <= #1 15'd679; + 8'd227 : rd_data <= #1 15'd1064; + 8'd228 : rd_data <= #1 15'd1015; + 8'd229 : rd_data <= #1 15'd1399; + 8'd230 : rd_data <= #1 15'd679; + 8'd231 : rd_data <= #1 15'd1064; + 8'd232 : rd_data <= #1 15'd1885; + 8'd233 : rd_data <= #1 15'd2269; + 8'd234 : rd_data <= #1 15'd1549; + 8'd235 : rd_data <= #1 15'd1933; + 8'd236 : rd_data <= #1 15'd1885; + 8'd237 : rd_data <= #1 15'd2269; + 8'd238 : rd_data <= #1 15'd1549; + 8'd239 : rd_data <= #1 15'd1933; + 8'd240 : rd_data <= #1 15'd2898; + 8'd241 : rd_data <= #1 15'd2693; + 8'd242 : rd_data <= #1 15'd3818; + 8'd243 : rd_data <= #1 15'd3612; + 8'd244 : rd_data <= #1 15'd767; + 8'd245 : rd_data <= #1 15'd561; + 8'd246 : rd_data <= #1 15'd1686; + 8'd247 : rd_data <= #1 15'd1481; + 8'd248 : rd_data <= #1 15'd7103; + 8'd249 : rd_data <= #1 15'd6898; + 8'd250 : rd_data <= #1 15'd8023; + 8'd251 : rd_data <= #1 15'd7817; + 8'd252 : rd_data <= #1 15'd4972; + 8'd253 : rd_data <= #1 15'd4766; + 8'd254 : rd_data <= #1 15'd5891; + 8'd255 : rd_data <= #1 15'd5686; + endcase // case(rd_addr) + end //if (strobe) + assign out_data[14:0]=reg_quadrant?-rd_data:rd_data; + sign_extend #(15,18) + ext_output (.in(out_data),.out(ext_out_data)); + +endmodule // rrc_coeff_ram_generated_0 + +//bw= 16 data_size= 5 abs_max= 32767 len= 16 +module rrc_coeff_ram_generated0_1 (input clock, input strobe, input [3:0] phase, input [4:0] in_data, output [15:0] out_data,output [17:0] ext_out_data); + +reg reg_quadrant; +wire quadrant=in_data[4]; +wire [7:0] rd_addr={phase,quadrant?~in_data[3:0]:in_data[3:0]}; +reg [15:0] rd_data; + + always @(posedge clock) + if (strobe) + begin + reg_quadrant <= #1 quadrant; + case (rd_addr) + 8'd0 : rd_data <= #1 -16'd21235; + 8'd1 : rd_data <= #1 16'd21903; + 8'd2 : rd_data <= #1 -16'd23385; + 8'd3 : rd_data <= #1 16'd19754; + 8'd4 : rd_data <= #1 -16'd19330; + 8'd5 : rd_data <= #1 16'd23809; + 8'd6 : rd_data <= #1 -16'd21479; + 8'd7 : rd_data <= #1 16'd21660; + 8'd8 : rd_data <= #1 -16'd22779; + 8'd9 : rd_data <= #1 16'd20360; + 8'd10 : rd_data <= #1 -16'd24928; + 8'd11 : rd_data <= #1 16'd18211; + 8'd12 : rd_data <= #1 -16'd20873; + 8'd13 : rd_data <= #1 16'd22266; + 8'd14 : rd_data <= #1 -16'd23022; + 8'd15 : rd_data <= #1 16'd20116; + 8'd16 : rd_data <= #1 -16'd22051; + 8'd17 : rd_data <= #1 -16'd4096; + 8'd18 : rd_data <= #1 16'd10606; + 8'd19 : rd_data <= #1 16'd28562; + 8'd20 : rd_data <= #1 -16'd30635; + 8'd21 : rd_data <= #1 -16'd12680; + 8'd22 : rd_data <= #1 16'd2022; + 8'd23 : rd_data <= #1 16'd19978; + 8'd24 : rd_data <= #1 -16'd17846; + 8'd25 : rd_data <= #1 16'd109; + 8'd26 : rd_data <= #1 16'd14811; + 8'd27 : rd_data <= #1 16'd32767; + 8'd28 : rd_data <= #1 -16'd26430; + 8'd29 : rd_data <= #1 -16'd8475; + 8'd30 : rd_data <= #1 16'd6227; + 8'd31 : rd_data <= #1 16'd24183; + 8'd32 : rd_data <= #1 -16'd23253; + 8'd33 : rd_data <= #1 16'd15012; + 8'd34 : rd_data <= #1 -16'd12934; + 8'd35 : rd_data <= #1 16'd25331; + 8'd36 : rd_data <= #1 -16'd26201; + 8'd37 : rd_data <= #1 16'd12064; + 8'd38 : rd_data <= #1 -16'd15882; + 8'd39 : rd_data <= #1 16'd22383; + 8'd40 : rd_data <= #1 -16'd22383; + 8'd41 : rd_data <= #1 16'd15882; + 8'd42 : rd_data <= #1 -16'd12064; + 8'd43 : rd_data <= #1 16'd26201; + 8'd44 : rd_data <= #1 -16'd25331; + 8'd45 : rd_data <= #1 16'd12934; + 8'd46 : rd_data <= #1 -16'd15012; + 8'd47 : rd_data <= #1 16'd23253; + 8'd48 : rd_data <= #1 -16'd20271; + 8'd49 : rd_data <= #1 -16'd16839; + 8'd50 : rd_data <= #1 16'd21616; + 8'd51 : rd_data <= #1 16'd25048; + 8'd52 : rd_data <= #1 -16'd26336; + 8'd53 : rd_data <= #1 -16'd22904; + 8'd54 : rd_data <= #1 16'd15550; + 8'd55 : rd_data <= #1 16'd18983; + 8'd56 : rd_data <= #1 -16'd16786; + 8'd57 : rd_data <= #1 -16'd13354; + 8'd58 : rd_data <= #1 16'd25101; + 8'd59 : rd_data <= #1 16'd28533; + 8'd60 : rd_data <= #1 -16'd22851; + 8'd61 : rd_data <= #1 -16'd19419; + 8'd62 : rd_data <= #1 16'd19035; + 8'd63 : rd_data <= #1 16'd22467; + 8'd64 : rd_data <= #1 -16'd22833; + 8'd65 : rd_data <= #1 16'd2818; + 8'd66 : rd_data <= #1 16'd2818; + 8'd67 : rd_data <= #1 16'd28469; + 8'd68 : rd_data <= #1 -16'd30389; + 8'd69 : rd_data <= #1 -16'd4738; + 8'd70 : rd_data <= #1 -16'd4738; + 8'd71 : rd_data <= #1 16'd20913; + 8'd72 : rd_data <= #1 -16'd19361; + 8'd73 : rd_data <= #1 16'd6290; + 8'd74 : rd_data <= #1 16'd6290; + 8'd75 : rd_data <= #1 16'd31941; + 8'd76 : rd_data <= #1 -16'd26917; + 8'd77 : rd_data <= #1 -16'd1266; + 8'd78 : rd_data <= #1 -16'd1266; + 8'd79 : rd_data <= #1 16'd24385; + 8'd80 : rd_data <= #1 -16'd22589; + 8'd81 : rd_data <= #1 16'd19298; + 8'd82 : rd_data <= #1 -16'd19157; + 8'd83 : rd_data <= #1 16'd22730; + 8'd84 : rd_data <= #1 -16'd22926; + 8'd85 : rd_data <= #1 16'd18961; + 8'd86 : rd_data <= #1 -16'd19494; + 8'd87 : rd_data <= #1 16'd22393; + 8'd88 : rd_data <= #1 -16'd23063; + 8'd89 : rd_data <= #1 16'd18824; + 8'd90 : rd_data <= #1 -16'd19631; + 8'd91 : rd_data <= #1 16'd22256; + 8'd92 : rd_data <= #1 -16'd23400; + 8'd93 : rd_data <= #1 16'd18487; + 8'd94 : rd_data <= #1 -16'd19968; + 8'd95 : rd_data <= #1 16'd21919; + 8'd96 : rd_data <= #1 -16'd21137; + 8'd97 : rd_data <= #1 -16'd10818; + 8'd98 : rd_data <= #1 16'd17128; + 8'd99 : rd_data <= #1 16'd27447; + 8'd100 : rd_data <= #1 -16'd29317; + 8'd101 : rd_data <= #1 -16'd18998; + 8'd102 : rd_data <= #1 16'd8947; + 8'd103 : rd_data <= #1 16'd19266; + 8'd104 : rd_data <= #1 -16'd16885; + 8'd105 : rd_data <= #1 -16'd6566; + 8'd106 : rd_data <= #1 16'd21380; + 8'd107 : rd_data <= #1 16'd31699; + 8'd108 : rd_data <= #1 -16'd25066; + 8'd109 : rd_data <= #1 -16'd14747; + 8'd110 : rd_data <= #1 16'd13199; + 8'd111 : rd_data <= #1 16'd23518; + 8'd112 : rd_data <= #1 -16'd23291; + 8'd113 : rd_data <= #1 16'd9367; + 8'd114 : rd_data <= #1 -16'd5335; + 8'd115 : rd_data <= #1 16'd27322; + 8'd116 : rd_data <= #1 -16'd28806; + 8'd117 : rd_data <= #1 16'd3851; + 8'd118 : rd_data <= #1 -16'd10851; + 8'd119 : rd_data <= #1 16'd21807; + 8'd120 : rd_data <= #1 -16'd21019; + 8'd121 : rd_data <= #1 16'd11639; + 8'd122 : rd_data <= #1 -16'd3063; + 8'd123 : rd_data <= #1 16'd29594; + 8'd124 : rd_data <= #1 -16'd26534; + 8'd125 : rd_data <= #1 16'd6123; + 8'd126 : rd_data <= #1 -16'd8579; + 8'd127 : rd_data <= #1 16'd24079; + 8'd128 : rd_data <= #1 -16'd21235; + 8'd129 : rd_data <= #1 16'd21903; + 8'd130 : rd_data <= #1 -16'd23385; + 8'd131 : rd_data <= #1 16'd19754; + 8'd132 : rd_data <= #1 -16'd19330; + 8'd133 : rd_data <= #1 16'd23809; + 8'd134 : rd_data <= #1 -16'd21479; + 8'd135 : rd_data <= #1 16'd21660; + 8'd136 : rd_data <= #1 -16'd22779; + 8'd137 : rd_data <= #1 16'd20360; + 8'd138 : rd_data <= #1 -16'd24928; + 8'd139 : rd_data <= #1 16'd18211; + 8'd140 : rd_data <= #1 -16'd20873; + 8'd141 : rd_data <= #1 16'd22266; + 8'd142 : rd_data <= #1 -16'd23022; + 8'd143 : rd_data <= #1 16'd20116; + 8'd144 : rd_data <= #1 -16'd22051; + 8'd145 : rd_data <= #1 -16'd4096; + 8'd146 : rd_data <= #1 16'd10606; + 8'd147 : rd_data <= #1 16'd28562; + 8'd148 : rd_data <= #1 -16'd30635; + 8'd149 : rd_data <= #1 -16'd12680; + 8'd150 : rd_data <= #1 16'd2022; + 8'd151 : rd_data <= #1 16'd19978; + 8'd152 : rd_data <= #1 -16'd17846; + 8'd153 : rd_data <= #1 16'd109; + 8'd154 : rd_data <= #1 16'd14811; + 8'd155 : rd_data <= #1 16'd32767; + 8'd156 : rd_data <= #1 -16'd26430; + 8'd157 : rd_data <= #1 -16'd8475; + 8'd158 : rd_data <= #1 16'd6227; + 8'd159 : rd_data <= #1 16'd24183; + 8'd160 : rd_data <= #1 -16'd23253; + 8'd161 : rd_data <= #1 16'd15012; + 8'd162 : rd_data <= #1 -16'd12934; + 8'd163 : rd_data <= #1 16'd25331; + 8'd164 : rd_data <= #1 -16'd26201; + 8'd165 : rd_data <= #1 16'd12064; + 8'd166 : rd_data <= #1 -16'd15882; + 8'd167 : rd_data <= #1 16'd22383; + 8'd168 : rd_data <= #1 -16'd22383; + 8'd169 : rd_data <= #1 16'd15882; + 8'd170 : rd_data <= #1 -16'd12064; + 8'd171 : rd_data <= #1 16'd26201; + 8'd172 : rd_data <= #1 -16'd25331; + 8'd173 : rd_data <= #1 16'd12934; + 8'd174 : rd_data <= #1 -16'd15012; + 8'd175 : rd_data <= #1 16'd23253; + 8'd176 : rd_data <= #1 -16'd20271; + 8'd177 : rd_data <= #1 -16'd16839; + 8'd178 : rd_data <= #1 16'd21616; + 8'd179 : rd_data <= #1 16'd25048; + 8'd180 : rd_data <= #1 -16'd26336; + 8'd181 : rd_data <= #1 -16'd22904; + 8'd182 : rd_data <= #1 16'd15550; + 8'd183 : rd_data <= #1 16'd18983; + 8'd184 : rd_data <= #1 -16'd16786; + 8'd185 : rd_data <= #1 -16'd13354; + 8'd186 : rd_data <= #1 16'd25101; + 8'd187 : rd_data <= #1 16'd28533; + 8'd188 : rd_data <= #1 -16'd22851; + 8'd189 : rd_data <= #1 -16'd19419; + 8'd190 : rd_data <= #1 16'd19035; + 8'd191 : rd_data <= #1 16'd22467; + 8'd192 : rd_data <= #1 -16'd22833; + 8'd193 : rd_data <= #1 16'd2818; + 8'd194 : rd_data <= #1 16'd2818; + 8'd195 : rd_data <= #1 16'd28469; + 8'd196 : rd_data <= #1 -16'd30389; + 8'd197 : rd_data <= #1 -16'd4738; + 8'd198 : rd_data <= #1 -16'd4738; + 8'd199 : rd_data <= #1 16'd20913; + 8'd200 : rd_data <= #1 -16'd19361; + 8'd201 : rd_data <= #1 16'd6290; + 8'd202 : rd_data <= #1 16'd6290; + 8'd203 : rd_data <= #1 16'd31941; + 8'd204 : rd_data <= #1 -16'd26917; + 8'd205 : rd_data <= #1 -16'd1266; + 8'd206 : rd_data <= #1 -16'd1266; + 8'd207 : rd_data <= #1 16'd24385; + 8'd208 : rd_data <= #1 -16'd22589; + 8'd209 : rd_data <= #1 16'd19298; + 8'd210 : rd_data <= #1 -16'd19157; + 8'd211 : rd_data <= #1 16'd22730; + 8'd212 : rd_data <= #1 -16'd22926; + 8'd213 : rd_data <= #1 16'd18961; + 8'd214 : rd_data <= #1 -16'd19494; + 8'd215 : rd_data <= #1 16'd22393; + 8'd216 : rd_data <= #1 -16'd23063; + 8'd217 : rd_data <= #1 16'd18824; + 8'd218 : rd_data <= #1 -16'd19631; + 8'd219 : rd_data <= #1 16'd22256; + 8'd220 : rd_data <= #1 -16'd23400; + 8'd221 : rd_data <= #1 16'd18487; + 8'd222 : rd_data <= #1 -16'd19968; + 8'd223 : rd_data <= #1 16'd21919; + 8'd224 : rd_data <= #1 -16'd21137; + 8'd225 : rd_data <= #1 -16'd10818; + 8'd226 : rd_data <= #1 16'd17128; + 8'd227 : rd_data <= #1 16'd27447; + 8'd228 : rd_data <= #1 -16'd29317; + 8'd229 : rd_data <= #1 -16'd18998; + 8'd230 : rd_data <= #1 16'd8947; + 8'd231 : rd_data <= #1 16'd19266; + 8'd232 : rd_data <= #1 -16'd16885; + 8'd233 : rd_data <= #1 -16'd6566; + 8'd234 : rd_data <= #1 16'd21380; + 8'd235 : rd_data <= #1 16'd31699; + 8'd236 : rd_data <= #1 -16'd25066; + 8'd237 : rd_data <= #1 -16'd14747; + 8'd238 : rd_data <= #1 16'd13199; + 8'd239 : rd_data <= #1 16'd23518; + 8'd240 : rd_data <= #1 -16'd23291; + 8'd241 : rd_data <= #1 16'd9367; + 8'd242 : rd_data <= #1 -16'd5335; + 8'd243 : rd_data <= #1 16'd27322; + 8'd244 : rd_data <= #1 -16'd28806; + 8'd245 : rd_data <= #1 16'd3851; + 8'd246 : rd_data <= #1 -16'd10851; + 8'd247 : rd_data <= #1 16'd21807; + 8'd248 : rd_data <= #1 -16'd21019; + 8'd249 : rd_data <= #1 16'd11639; + 8'd250 : rd_data <= #1 -16'd3063; + 8'd251 : rd_data <= #1 16'd29594; + 8'd252 : rd_data <= #1 -16'd26534; + 8'd253 : rd_data <= #1 16'd6123; + 8'd254 : rd_data <= #1 -16'd8579; + 8'd255 : rd_data <= #1 16'd24079; + endcase // case(rd_addr) + end //if (strobe) + assign out_data[15:0]=reg_quadrant?-rd_data:rd_data; + sign_extend #(16,18) + ext_output (.in(out_data),.out(ext_out_data)); + +endmodule // rrc_coeff_ram_generated_1 + +//bw= 11 data_size= 1 abs_max= 649 len= 1 +module rrc_coeff_ram_generated0_2 (input clock, input strobe, input [3:0] phase, input [0:0] in_data, output [10:0] out_data,output [17:0] ext_out_data); + +reg reg_quadrant; +wire quadrant=in_data[0]; +wire [3:0] rd_addr=phase; +reg [10:0] rd_data; + + always @(posedge clock) + if (strobe) + begin + reg_quadrant <= #1 quadrant; + case (rd_addr) + 4'd0 : rd_data <= #1 11'd347; + 4'd1 : rd_data <= #1 -11'd460; + 4'd2 : rd_data <= #1 11'd168; + 4'd3 : rd_data <= #1 -11'd649; + 4'd4 : rd_data <= #1 -11'd250; + 4'd5 : rd_data <= #1 11'd298; + 4'd6 : rd_data <= #1 -11'd607; + 4'd7 : rd_data <= #1 -11'd26; + 4'd8 : rd_data <= #1 11'd347; + 4'd9 : rd_data <= #1 -11'd460; + 4'd10 : rd_data <= #1 11'd168; + 4'd11 : rd_data <= #1 -11'd649; + 4'd12 : rd_data <= #1 -11'd250; + 4'd13 : rd_data <= #1 11'd298; + 4'd14 : rd_data <= #1 -11'd607; + 4'd15 : rd_data <= #1 -11'd26; + endcase // case(rd_addr) + end //if (strobe) + assign out_data[10:0]=reg_quadrant?-rd_data:rd_data; + sign_extend #(11,18) + ext_output (.in(out_data),.out(ext_out_data)); + +endmodule // rrc_coeff_ram_generated_2 + +//bw_memory [4, 4, 0] data_size 5 +module frac_interp_0 + + (input clock, input reset, input enable, + output reg strobe_in, input strobe_out, + input wire [4:0] tx_shift, + input wire [15:0] signal_in, + output reg [15:0] signal_out); + +reg [3:0] phase;//max 16 phases + +reg [3:0] in_count;//16 bits in every register + +reg [15:0] input_16; + +reg [15:0] shift_16_0; +wire get_bit= (phase==4'd1) || (phase==4'd3) || (phase==4'd4) || (phase==4'd6) || (phase==4'd7) || (phase==4'd9) || (phase==4'd11) || (phase==4'd12) || (phase==4'd14) || (phase==4'd15); + + always @(posedge clock) + if (reset) + begin + strobe_in <= #1 0;// Reset + in_count <=#1 0; + input_16 <= #1 0; + + shift_16_0 <= #1 0; + + end //if (reset) + else //if (reset) + begin + if(enable & strobe_out & get_bit & (in_count == 4'd15)) + strobe_in <=#1 1'd1;//Only works if output of previous stage is registered and only updates on this strobe_in + else // if(strobe_in) //input a new 16 bit word and shift all regs 16 bit to the right= to next register) + strobe_in <= #1 0;//notice the else is always executed, even if there is no strobe_out so strobe_in will only be high for 1 clock + + if (enable & strobe_out) + begin + if ( get_bit) + + begin //shift input 1 bit to the left + if(in_count == 4'd15) //(strobe_in) //if(in_count == 4'd0) + begin + //strobe_in <=#1 1'd1;//Only works if output of previous stage is registered and only updates on this strobe_in + input_16 <= #1 signal_in; + end //if(in_count == 4'd0) + else //if(in_count == 4'd0) + begin + input_16 <= #1 {1'd0,input_16[15:1]};//just shift right //MDVH 14feb2007 + //input_16 <= #1 {input_16[14:0],1'd0};//just shift left //MDVH 14feb2007 + end // if(in_count == 4'd0) else + //shift_16_0 <= #1 {shift_16_0[14:0],input_16[15]};//MDVH 14feb2007 + shift_16_0 <= #1 {input_16[0],shift_16_0[15:1]};//MDVH 14feb2007 + + + in_count <= #1 in_count+4'd1; + end //if ((phase==.... + end //if (enable & strobe_out) + end // if (reset) else + + always @(posedge clock) + if (reset) + phase <=#1 0; + else if (enable & strobe_out) + phase <=#1 phase + 4'd1;//phase will roll-over to zero and start again + + +wire [4:0] data_0; +wire [4:0] data_1; +wire [0:0] data_2; +assign data_2=shift_16_0[10:10]; +assign data_1=shift_16_0[9:5]; +assign data_0=shift_16_0[4:0]; +wire [17:0] sum_0; +wire [17:0] sum_1; +wire [17:0] sum_2; +wire [17:0] sum_3; +assign sum_3=0; +reg [17:0] sum_all; + +//wire [15:0] sum_all_16bit; + + rrc_coeff_ram_generated0_0 rrc_coeff_ram_0 ( .clock(clock),.strobe(strobe_out),.phase(phase),.in_data(data_0),.out_data(),.ext_out_data(sum_0) ); + rrc_coeff_ram_generated0_1 rrc_coeff_ram_1 ( .clock(clock),.strobe(strobe_out),.phase(phase),.in_data(data_1),.out_data(),.ext_out_data(sum_1) ); + rrc_coeff_ram_generated0_2 rrc_coeff_ram_2 ( .clock(clock),.strobe(strobe_out),.phase(phase),.in_data(data_2),.out_data(),.ext_out_data(sum_2) ); +//assign sum_all= sum_0 + sum_1 + sum_2; +reg [17:0] sum_01; +reg [17:0] sum_23; +reg [17:0] sum_0123; + + always @(posedge clock) + if (reset) + begin + + sum_01 <= #1 0; + sum_23 <= #1 0; + sum_0123 <= #1 0; + + sum_all <=#1 0; + signal_out <= #1 0; + end + else if (enable & strobe_out) + begin + + sum_01 <= #1 sum_0+sum_1; + sum_23 <= #1 sum_2+sum_3; + sum_0123 <= #1 sum_01+sum_23; + sum_all <= #1 sum_0123; + + case(tx_shift) + //5'd0 : signal_out <= #1 round_16(sum_all);//no gain reduce + 5'd0 : signal_out <= #1 { sum_all[16:1] + (sum_all[17] & ( sum_all[0] )) }; + 5'd1 : signal_out <= #1 { sum_all[17:2] + (sum_all[17] & (|sum_all[1:0])) }; + 5'd2 : signal_out <= #1 { {{(1){sum_all[17]}}, sum_all[17:3]} + (sum_all[17] & (|sum_all[2:0])) }; + 5'd3 : signal_out <= #1 { {{(2){sum_all[17]}}, sum_all[17:4]} + (sum_all[17] & (|sum_all[3:0])) }; + 5'd4 : signal_out <= #1 { {{(3){sum_all[17]}}, sum_all[17:5]} + (sum_all[17] & (|sum_all[4:0])) }; + 5'd5 : signal_out <= #1 { {{(4){sum_all[17]}}, sum_all[17:6]} + (sum_all[17] & (|sum_all[5:0])) }; + 5'd6 : signal_out <= #1 { {{(5){sum_all[17]}}, sum_all[17:7]} + (sum_all[17] & (|sum_all[6:0])) }; + 5'd7 : signal_out <= #1 { {{(6){sum_all[17]}}, sum_all[17:8]} + (sum_all[17] & (|sum_all[7:0])) }; + 5'd8 : signal_out <= #1 { {{(7){sum_all[17]}}, sum_all[17:9]} + (sum_all[17] & (|sum_all[8:0])) }; + 5'd9 : signal_out <= #1 { {{(8){sum_all[17]}}, sum_all[17:10]} + (sum_all[17] & (|sum_all[9:0])) }; + 5'd10 : signal_out <= #1 { {{(9){sum_all[17]}},sum_all[17:11]} + (sum_all[17] & (|sum_all[10:0]))}; + 5'd11 : signal_out <= #1 { {{(10){sum_all[17]}},sum_all[17:12]} + (sum_all[17] & (|sum_all[11:0]))}; + 5'd12 : signal_out <= #1 { {{(11){sum_all[17]}},sum_all[17:13]} + (sum_all[17] & (|sum_all[12:0]))}; + 5'd13 : signal_out <= #1 { {{(12){sum_all[17]}},sum_all[17:14]} + (sum_all[17] & (|sum_all[13:0]))}; + 5'd14 : signal_out <= #1 { {{(13){sum_all[17]}},sum_all[17:15]} + (sum_all[17] & (|sum_all[14:0]))}; + 5'd15 : signal_out <= #1 { {{(14){sum_all[17]}},sum_all[17:16]} + (sum_all[17] & (|sum_all[15:0]))}; + + -5'd1 : signal_out <= #1 {sum_all[15:0] }; + -5'd2 : signal_out <= #1 {sum_all[14:0] ,{(1){1'b0}}}; + -5'd3 : signal_out <= #1 {sum_all[13:0] ,{(2){1'b0}}}; + -5'd4 : signal_out <= #1 {sum_all[12:0] ,{(3){1'b0}}}; + -5'd5 : signal_out <= #1 {sum_all[11:0] ,{(4){1'b0}}}; + -5'd6 : signal_out <= #1 {sum_all[10:0] ,{(5){1'b0}}}; + -5'd7 : signal_out <= #1 {sum_all[9:0] ,{(6){1'b0}}}; + -5'd8 : signal_out <= #1 {sum_all[8:0] ,{(7){1'b0}}}; + -5'd9 : signal_out <= #1 {sum_all[7:0] ,{(8){1'b0}}}; + -5'd10 : signal_out <= #1 {sum_all[6:0] ,{(9){1'b0}}}; + -5'd11 : signal_out <= #1 {sum_all[5:0] ,{(10){1'b0}}}; + -5'd12 : signal_out <= #1 {sum_all[4:0] ,{(11){1'b0}}}; + -5'd13 : signal_out <= #1 {sum_all[3:0] ,{(12){1'b0}}}; + -5'd14 : signal_out <= #1 {sum_all[2:0] ,{(13){1'b0}}}; + -5'd15 : signal_out <= #1 {sum_all[1:0] ,{(14){1'b0}}}; + + default : signal_out <= #1 { sum_all[16:1] + (sum_all[17] & ( sum_all[0] )) }; + //signal_out <= #1 { sum_all[17:2] + (sum_all[17] & (|sum_all[1:0])) }; + endcase // case(shift) + + //sum_all_14bit <= #1 sum_0123[16:3] + (sum_0123[16] & |sum_0123[2:0]);//round to 14 bit (reduce gain by 2 bit = 12 dB) + + //signal_out <= #1 round_16(sum_all);//no gain reduce + //signal_out <= #1 {{(2){sum_all_14bit[13]}},sum_all_14bit};//sign_extend to 16 bit (gain reduced by 2 bit = 12 dB) + + end //else if (enable & strobe_out) + + +/*assign sum_all_16bit=round_16(sum_all); +//register the output to ease timing of the DDR DAC output + always @(posedge clock or posedge reset) + if (reset) + signal_out <= #1 0; // Reset + else + signal_out <= #1 sum_all_16bit; +*/ +//round to 16 bit +// function [15:0] round_16; +// input [16:0] in_val; +// round_16 = in_val[16:1] + (in_val[16] & |in_val[0]);//round_16 = in_val[16:1] + (in_val[16] & in_val[0]) +// endfunction // round_16 + + +endmodule //module frac_interp_0 Index: usrp/fpga/sdr_lib/frac_interp_alpha0.2_int16_dec10_DACint4X_chan1.v =================================================================== --- usrp/fpga/sdr_lib/frac_interp_alpha0.2_int16_dec10_DACint4X_chan1.v (revision 0) +++ usrp/fpga/sdr_lib/frac_interp_alpha0.2_int16_dec10_DACint4X_chan1.v (revision 0) @@ -0,0 +1,879 @@ +// -*- verilog -*- +// +// Polyphase interpolating Root-Raised-Cosine filter +// +// Copyright (C) 2007 Martin Dudok van Heel +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// +// Polyphase interpolating Root-Raised-Cosine filter +// Interpolation ratio can be fractional (float) +// +// This file was generated by ./generate_frac_interp_05nov2007.py at 2007-11-08 00:15:23.296453 +// Written by Martin Dudok van Heel, 2007 +// Olifantasia +// +// Contact: http://www.olifantasia.com/gnuradio/contact.gif or nldudok1_olifantasia_com +// http://www.olifantasia.com +// +// This file can be used to build a special purpose firmware for the USRP +// USRP = Universal Software Radio Peripheral +// This special purpose firmware in combination with the GnuRadio framework can be used to create a high speed QPSK transmitter +// Depending on the decimation and interpolation factors used, the symbolrate can be from 2 to 20 Msymbols/sec +// The corresponding QPSK bitrate is 4 to 40 Mbit/sec +// alpha= 0.2 +// interpolation = 16.0 decimation= 10.0 interp_ratio= 1.6 decim_ratio= 0.625 +// symbol rate = 20.0 Msymbol/sec +// QPSK bitrate = 40.0 Mbit/sec +// +//fractional ntaps 17.6 +//ntaps_per_filter= 11 +//nfilters= 16 +// s f incr d_mu ii oo step +// 0.0 0.0 0 0.0 0 0 0 +// 0.625 0.0 0 0.625 0 1 1 +// 1.25 1.0 1 0.25 1 2 2 +// 0.875 0.0 0 0.875 1 3 3 +// 1.5 1.0 1 0.5 2 4 4 +// 1.125 1.0 1 0.125 3 5 5 +// 0.75 0.0 0 0.75 3 6 6 +// 1.375 1.0 1 0.375 4 7 7 +// 1.0 1.0 1 0.0 5 8 8 +// 0.625 0.0 0 0.625 5 9 9 +// 1.25 1.0 1 0.25 6 10 10 +// 0.875 0.0 0 0.875 6 11 11 +// 1.5 1.0 1 0.5 7 12 12 +// 1.125 1.0 1 0.125 8 13 13 +// 0.75 0.0 0 0.75 8 14 14 +// 1.375 1.0 1 0.375 9 15 15 +//poly_filter[ 0 ] = +// [-0.016952886801492591, 0.027320014270136073, -0.037678710298681584, 0.04652154604550536, -0.052473019541496996, 1.0531792715130162, -0.052473019541496996, 0.04652154604550536, -0.037678710298681584, 0.027320014270136073, -0.016952886801492591] + +//poly_filter[ 1 ] = +// [0.0064053452259068928, 0.0012467941820681503, -0.019236656305587702, 0.055471404769445419, -0.134652938078933, 0.43836544769923702, 0.79729550875966892, -0.20956911563411504, 0.10265723635479067, -0.052044187277807373, 0.022441577548409291] + +//poly_filter[ 2 ] = +// [-0.011121268801005637, 0.029638149747377985, -0.058136370658318372, 0.10379850880938603, -0.19972149237265682, 0.93418657928447435, 0.25192427285271296, -0.071978363672203727, 0.021231513165556354, -7.7873837828280443e-17, -0.0081946191165304366] + +//poly_filter[ 3 ] = +// [0.0098336035607602488, -0.014526954900680811, 0.016352547900186802, -0.01157728372979675, -0.0082269202043394191, 0.083792247178060913, 1.0226126363290351, -0.1480767079436732, 0.085077499291207725, -0.053624731253201059, 0.031699112977245862] + +//poly_filter[ 4 ] = +// [0.0012862557726307691, 0.012187354345710392, -0.037881534084307146, 0.08476443400746296, -0.18447589163766012, 0.62623488448318076, 0.62623488448318076, -0.18447589163766012, 0.08476443400746296, -0.037881534084307146, 0.012187354345710392] + +//poly_filter[ 5 ] = +// [-0.015543521630860075, 0.031699112977245862, -0.053624731253201059, 0.085077499291207725, -0.1480767079436732, 1.0226126363290351, 0.083792247178060913, -0.0082269202043394191, -0.01157728372979675, 0.016352547900186802, -0.014526954900680811] + +//poly_filter[ 6 ] = +// [0.0093884822181135134, -0.0081946191165304366, -7.7873837828280443e-17, 0.021231513165556354, -0.071978363672203727, 0.25192427285271296, 0.93418657928447435, -0.19972149237265682, 0.10379850880938603, -0.058136370658318372, 0.029638149747377985] + +//poly_filter[ 7 ] = +// [-0.0050099408373175149, 0.022441577548409291, -0.052044187277807373, 0.10265723635479067, -0.20956911563411504, 0.79729550875966892, 0.43836544769923702, -0.134652938078933, 0.055471404769445419, -0.019236656305587702, 0.0012467941820681503] + +//poly_filter[ 8 ] = +// [-0.016952886801492591, 0.027320014270136073, -0.037678710298681584, 0.04652154604550536, -0.052473019541496996, 1.0531792715130162, -0.052473019541496996, 0.04652154604550536, -0.037678710298681584, 0.027320014270136073, -0.016952886801492591] + +//poly_filter[ 9 ] = +// [0.0064053452259068928, 0.0012467941820681503, -0.019236656305587702, 0.055471404769445419, -0.134652938078933, 0.43836544769923702, 0.79729550875966892, -0.20956911563411504, 0.10265723635479067, -0.052044187277807373, 0.022441577548409291] + +//poly_filter[ 10 ] = +// [-0.011121268801005637, 0.029638149747377985, -0.058136370658318372, 0.10379850880938603, -0.19972149237265682, 0.93418657928447435, 0.25192427285271296, -0.071978363672203727, 0.021231513165556354, -7.7873837828280443e-17, -0.0081946191165304366] + +//poly_filter[ 11 ] = +// [0.0098336035607602488, -0.014526954900680811, 0.016352547900186802, -0.01157728372979675, -0.0082269202043394191, 0.083792247178060913, 1.0226126363290351, -0.1480767079436732, 0.085077499291207725, -0.053624731253201059, 0.031699112977245862] + +//poly_filter[ 12 ] = +// [0.0012862557726307691, 0.012187354345710392, -0.037881534084307146, 0.08476443400746296, -0.18447589163766012, 0.62623488448318076, 0.62623488448318076, -0.18447589163766012, 0.08476443400746296, -0.037881534084307146, 0.012187354345710392] + +//poly_filter[ 13 ] = +// [-0.015543521630860075, 0.031699112977245862, -0.053624731253201059, 0.085077499291207725, -0.1480767079436732, 1.0226126363290351, 0.083792247178060913, -0.0082269202043394191, -0.01157728372979675, 0.016352547900186802, -0.014526954900680811] + +//poly_filter[ 14 ] = +// [0.0093884822181135134, -0.0081946191165304366, -7.7873837828280443e-17, 0.021231513165556354, -0.071978363672203727, 0.25192427285271296, 0.93418657928447435, -0.19972149237265682, 0.10379850880938603, -0.058136370658318372, 0.029638149747377985] + +//poly_filter[ 15 ] = +// [-0.0050099408373175149, 0.022441577548409291, -0.052044187277807373, 0.10265723635479067, -0.20956911563411504, 0.79729550875966892, 0.43836544769923702, -0.134652938078933, 0.055471404769445419, -0.019236656305587702, 0.0012467941820681503] + +// total_ntaps= 176 +// ntaps_per_filter= 11 +// nfilters= 16 +// filter resolution= 16 bits +// +//data_size= 5 phase_size= 4 +//abs_max= 1.59993149573 abs_max_16bit= 32767 signed_max_16bit= 32767 signed_min_16bit= -30635 +//nmemories= 3 +//incr_list = [1, 3, 4, 6, 7, 9, 11, 12, 14, 15] +//bw= 15 data_size= 5 abs_max= 8242 len= 16 +module rrc_coeff_ram_generated1_0 (input clock, input strobe, input [3:0] phase, input [4:0] in_data, output [14:0] out_data,output [17:0] ext_out_data); + +reg reg_quadrant; +wire quadrant=in_data[4]; +wire [7:0] rd_addr={phase,quadrant?~in_data[3:0]:in_data[3:0]}; +reg [14:0] rd_data; + + always @(posedge clock) + if (strobe) + begin + reg_quadrant <= #1 quadrant; + case (rd_addr) + 8'd0 : rd_data <= #1 15'd681; + 8'd1 : rd_data <= #1 -15'd13; + 8'd2 : rd_data <= #1 15'd1800; + 8'd3 : rd_data <= #1 15'd1106; + 8'd4 : rd_data <= #1 -15'd862; + 8'd5 : rd_data <= #1 -15'd1557; + 8'd6 : rd_data <= #1 15'd257; + 8'd7 : rd_data <= #1 -15'd437; + 8'd8 : rd_data <= #1 15'd2587; + 8'd9 : rd_data <= #1 15'd1892; + 8'd10 : rd_data <= #1 15'd3706; + 8'd11 : rd_data <= #1 15'd3011; + 8'd12 : rd_data <= #1 15'd1043; + 8'd13 : rd_data <= #1 15'd349; + 8'd14 : rd_data <= #1 15'd2162; + 8'd15 : rd_data <= #1 15'd1468; + 8'd16 : rd_data <= #1 15'd1859; + 8'd17 : rd_data <= #1 15'd2121; + 8'd18 : rd_data <= #1 15'd1910; + 8'd19 : rd_data <= #1 15'd2172; + 8'd20 : rd_data <= #1 15'd1071; + 8'd21 : rd_data <= #1 15'd1333; + 8'd22 : rd_data <= #1 15'd1122; + 8'd23 : rd_data <= #1 15'd1384; + 8'd24 : rd_data <= #1 15'd4131; + 8'd25 : rd_data <= #1 15'd4393; + 8'd26 : rd_data <= #1 15'd4182; + 8'd27 : rd_data <= #1 15'd4444; + 8'd28 : rd_data <= #1 15'd3343; + 8'd29 : rd_data <= #1 15'd3605; + 8'd30 : rd_data <= #1 15'd3394; + 8'd31 : rd_data <= #1 15'd3657; + 8'd32 : rd_data <= #1 15'd2776; + 8'd33 : rd_data <= #1 15'd2320; + 8'd34 : rd_data <= #1 15'd3990; + 8'd35 : rd_data <= #1 15'd3534; + 8'd36 : rd_data <= #1 15'd395; + 8'd37 : rd_data <= #1 -15'd61; + 8'd38 : rd_data <= #1 15'd1609; + 8'd39 : rd_data <= #1 15'd1153; + 8'd40 : rd_data <= #1 15'd7028; + 8'd41 : rd_data <= #1 15'd6572; + 8'd42 : rd_data <= #1 15'd8242; + 8'd43 : rd_data <= #1 15'd7786; + 8'd44 : rd_data <= #1 15'd4646; + 8'd45 : rd_data <= #1 15'd4191; + 8'd46 : rd_data <= #1 15'd5860; + 8'd47 : rd_data <= #1 15'd5405; + 8'd48 : rd_data <= #1 15'd167; + 8'd49 : rd_data <= #1 15'd570; + 8'd50 : rd_data <= #1 -15'd428; + 8'd51 : rd_data <= #1 -15'd25; + 8'd52 : rd_data <= #1 15'd837; + 8'd53 : rd_data <= #1 15'd1239; + 8'd54 : rd_data <= #1 15'd242; + 8'd55 : rd_data <= #1 15'd644; + 8'd56 : rd_data <= #1 -15'd307; + 8'd57 : rd_data <= #1 15'd95; + 8'd58 : rd_data <= #1 -15'd902; + 8'd59 : rd_data <= #1 -15'd500; + 8'd60 : rd_data <= #1 15'd362; + 8'd61 : rd_data <= #1 15'd765; + 8'd62 : rd_data <= #1 -15'd233; + 8'd63 : rd_data <= #1 15'd170; + 8'd64 : rd_data <= #1 15'd2542; + 8'd65 : rd_data <= #1 15'd2595; + 8'd66 : rd_data <= #1 15'd3041; + 8'd67 : rd_data <= #1 15'd3094; + 8'd68 : rd_data <= #1 15'd990; + 8'd69 : rd_data <= #1 15'd1043; + 8'd70 : rd_data <= #1 15'd1490; + 8'd71 : rd_data <= #1 15'd1542; + 8'd72 : rd_data <= #1 15'd6014; + 8'd73 : rd_data <= #1 15'd6067; + 8'd74 : rd_data <= #1 15'd6513; + 8'd75 : rd_data <= #1 15'd6566; + 8'd76 : rd_data <= #1 15'd4462; + 8'd77 : rd_data <= #1 15'd4515; + 8'd78 : rd_data <= #1 15'd4962; + 8'd79 : rd_data <= #1 15'd5014; + 8'd80 : rd_data <= #1 15'd2058; + 8'd81 : rd_data <= #1 15'd1421; + 8'd82 : rd_data <= #1 15'd3356; + 8'd83 : rd_data <= #1 15'd2719; + 8'd84 : rd_data <= #1 -15'd139; + 8'd85 : rd_data <= #1 -15'd776; + 8'd86 : rd_data <= #1 15'd1160; + 8'd87 : rd_data <= #1 15'd523; + 8'd88 : rd_data <= #1 15'd5542; + 8'd89 : rd_data <= #1 15'd4906; + 8'd90 : rd_data <= #1 15'd6841; + 8'd91 : rd_data <= #1 15'd6204; + 8'd92 : rd_data <= #1 15'd3346; + 8'd93 : rd_data <= #1 15'd2709; + 8'd94 : rd_data <= #1 15'd4644; + 8'd95 : rd_data <= #1 15'd4008; + 8'd96 : rd_data <= #1 15'd1015; + 8'd97 : rd_data <= #1 15'd1399; + 8'd98 : rd_data <= #1 15'd679; + 8'd99 : rd_data <= #1 15'd1064; + 8'd100 : rd_data <= #1 15'd1015; + 8'd101 : rd_data <= #1 15'd1399; + 8'd102 : rd_data <= #1 15'd679; + 8'd103 : rd_data <= #1 15'd1064; + 8'd104 : rd_data <= #1 15'd1885; + 8'd105 : rd_data <= #1 15'd2269; + 8'd106 : rd_data <= #1 15'd1549; + 8'd107 : rd_data <= #1 15'd1933; + 8'd108 : rd_data <= #1 15'd1885; + 8'd109 : rd_data <= #1 15'd2269; + 8'd110 : rd_data <= #1 15'd1549; + 8'd111 : rd_data <= #1 15'd1933; + 8'd112 : rd_data <= #1 15'd2898; + 8'd113 : rd_data <= #1 15'd2693; + 8'd114 : rd_data <= #1 15'd3818; + 8'd115 : rd_data <= #1 15'd3612; + 8'd116 : rd_data <= #1 15'd767; + 8'd117 : rd_data <= #1 15'd561; + 8'd118 : rd_data <= #1 15'd1686; + 8'd119 : rd_data <= #1 15'd1481; + 8'd120 : rd_data <= #1 15'd7103; + 8'd121 : rd_data <= #1 15'd6898; + 8'd122 : rd_data <= #1 15'd8023; + 8'd123 : rd_data <= #1 15'd7817; + 8'd124 : rd_data <= #1 15'd4972; + 8'd125 : rd_data <= #1 15'd4766; + 8'd126 : rd_data <= #1 15'd5891; + 8'd127 : rd_data <= #1 15'd5686; + 8'd128 : rd_data <= #1 15'd681; + 8'd129 : rd_data <= #1 -15'd13; + 8'd130 : rd_data <= #1 15'd1800; + 8'd131 : rd_data <= #1 15'd1106; + 8'd132 : rd_data <= #1 -15'd862; + 8'd133 : rd_data <= #1 -15'd1557; + 8'd134 : rd_data <= #1 15'd257; + 8'd135 : rd_data <= #1 -15'd437; + 8'd136 : rd_data <= #1 15'd2587; + 8'd137 : rd_data <= #1 15'd1892; + 8'd138 : rd_data <= #1 15'd3706; + 8'd139 : rd_data <= #1 15'd3011; + 8'd140 : rd_data <= #1 15'd1043; + 8'd141 : rd_data <= #1 15'd349; + 8'd142 : rd_data <= #1 15'd2162; + 8'd143 : rd_data <= #1 15'd1468; + 8'd144 : rd_data <= #1 15'd1859; + 8'd145 : rd_data <= #1 15'd2121; + 8'd146 : rd_data <= #1 15'd1910; + 8'd147 : rd_data <= #1 15'd2172; + 8'd148 : rd_data <= #1 15'd1071; + 8'd149 : rd_data <= #1 15'd1333; + 8'd150 : rd_data <= #1 15'd1122; + 8'd151 : rd_data <= #1 15'd1384; + 8'd152 : rd_data <= #1 15'd4131; + 8'd153 : rd_data <= #1 15'd4393; + 8'd154 : rd_data <= #1 15'd4182; + 8'd155 : rd_data <= #1 15'd4444; + 8'd156 : rd_data <= #1 15'd3343; + 8'd157 : rd_data <= #1 15'd3605; + 8'd158 : rd_data <= #1 15'd3394; + 8'd159 : rd_data <= #1 15'd3657; + 8'd160 : rd_data <= #1 15'd2776; + 8'd161 : rd_data <= #1 15'd2320; + 8'd162 : rd_data <= #1 15'd3990; + 8'd163 : rd_data <= #1 15'd3534; + 8'd164 : rd_data <= #1 15'd395; + 8'd165 : rd_data <= #1 -15'd61; + 8'd166 : rd_data <= #1 15'd1609; + 8'd167 : rd_data <= #1 15'd1153; + 8'd168 : rd_data <= #1 15'd7028; + 8'd169 : rd_data <= #1 15'd6572; + 8'd170 : rd_data <= #1 15'd8242; + 8'd171 : rd_data <= #1 15'd7786; + 8'd172 : rd_data <= #1 15'd4646; + 8'd173 : rd_data <= #1 15'd4191; + 8'd174 : rd_data <= #1 15'd5860; + 8'd175 : rd_data <= #1 15'd5405; + 8'd176 : rd_data <= #1 15'd167; + 8'd177 : rd_data <= #1 15'd570; + 8'd178 : rd_data <= #1 -15'd428; + 8'd179 : rd_data <= #1 -15'd25; + 8'd180 : rd_data <= #1 15'd837; + 8'd181 : rd_data <= #1 15'd1239; + 8'd182 : rd_data <= #1 15'd242; + 8'd183 : rd_data <= #1 15'd644; + 8'd184 : rd_data <= #1 -15'd307; + 8'd185 : rd_data <= #1 15'd95; + 8'd186 : rd_data <= #1 -15'd902; + 8'd187 : rd_data <= #1 -15'd500; + 8'd188 : rd_data <= #1 15'd362; + 8'd189 : rd_data <= #1 15'd765; + 8'd190 : rd_data <= #1 -15'd233; + 8'd191 : rd_data <= #1 15'd170; + 8'd192 : rd_data <= #1 15'd2542; + 8'd193 : rd_data <= #1 15'd2595; + 8'd194 : rd_data <= #1 15'd3041; + 8'd195 : rd_data <= #1 15'd3094; + 8'd196 : rd_data <= #1 15'd990; + 8'd197 : rd_data <= #1 15'd1043; + 8'd198 : rd_data <= #1 15'd1490; + 8'd199 : rd_data <= #1 15'd1542; + 8'd200 : rd_data <= #1 15'd6014; + 8'd201 : rd_data <= #1 15'd6067; + 8'd202 : rd_data <= #1 15'd6513; + 8'd203 : rd_data <= #1 15'd6566; + 8'd204 : rd_data <= #1 15'd4462; + 8'd205 : rd_data <= #1 15'd4515; + 8'd206 : rd_data <= #1 15'd4962; + 8'd207 : rd_data <= #1 15'd5014; + 8'd208 : rd_data <= #1 15'd2058; + 8'd209 : rd_data <= #1 15'd1421; + 8'd210 : rd_data <= #1 15'd3356; + 8'd211 : rd_data <= #1 15'd2719; + 8'd212 : rd_data <= #1 -15'd139; + 8'd213 : rd_data <= #1 -15'd776; + 8'd214 : rd_data <= #1 15'd1160; + 8'd215 : rd_data <= #1 15'd523; + 8'd216 : rd_data <= #1 15'd5542; + 8'd217 : rd_data <= #1 15'd4906; + 8'd218 : rd_data <= #1 15'd6841; + 8'd219 : rd_data <= #1 15'd6204; + 8'd220 : rd_data <= #1 15'd3346; + 8'd221 : rd_data <= #1 15'd2709; + 8'd222 : rd_data <= #1 15'd4644; + 8'd223 : rd_data <= #1 15'd4008; + 8'd224 : rd_data <= #1 15'd1015; + 8'd225 : rd_data <= #1 15'd1399; + 8'd226 : rd_data <= #1 15'd679; + 8'd227 : rd_data <= #1 15'd1064; + 8'd228 : rd_data <= #1 15'd1015; + 8'd229 : rd_data <= #1 15'd1399; + 8'd230 : rd_data <= #1 15'd679; + 8'd231 : rd_data <= #1 15'd1064; + 8'd232 : rd_data <= #1 15'd1885; + 8'd233 : rd_data <= #1 15'd2269; + 8'd234 : rd_data <= #1 15'd1549; + 8'd235 : rd_data <= #1 15'd1933; + 8'd236 : rd_data <= #1 15'd1885; + 8'd237 : rd_data <= #1 15'd2269; + 8'd238 : rd_data <= #1 15'd1549; + 8'd239 : rd_data <= #1 15'd1933; + 8'd240 : rd_data <= #1 15'd2898; + 8'd241 : rd_data <= #1 15'd2693; + 8'd242 : rd_data <= #1 15'd3818; + 8'd243 : rd_data <= #1 15'd3612; + 8'd244 : rd_data <= #1 15'd767; + 8'd245 : rd_data <= #1 15'd561; + 8'd246 : rd_data <= #1 15'd1686; + 8'd247 : rd_data <= #1 15'd1481; + 8'd248 : rd_data <= #1 15'd7103; + 8'd249 : rd_data <= #1 15'd6898; + 8'd250 : rd_data <= #1 15'd8023; + 8'd251 : rd_data <= #1 15'd7817; + 8'd252 : rd_data <= #1 15'd4972; + 8'd253 : rd_data <= #1 15'd4766; + 8'd254 : rd_data <= #1 15'd5891; + 8'd255 : rd_data <= #1 15'd5686; + endcase // case(rd_addr) + end //if (strobe) + assign out_data[14:0]=reg_quadrant?-rd_data:rd_data; + sign_extend #(15,18) + ext_output (.in(out_data),.out(ext_out_data)); + +endmodule // rrc_coeff_ram_generated_0 + +//bw= 16 data_size= 5 abs_max= 32767 len= 16 +module rrc_coeff_ram_generated1_1 (input clock, input strobe, input [3:0] phase, input [4:0] in_data, output [15:0] out_data,output [17:0] ext_out_data); + +reg reg_quadrant; +wire quadrant=in_data[4]; +wire [7:0] rd_addr={phase,quadrant?~in_data[3:0]:in_data[3:0]}; +reg [15:0] rd_data; + + always @(posedge clock) + if (strobe) + begin + reg_quadrant <= #1 quadrant; + case (rd_addr) + 8'd0 : rd_data <= #1 -16'd21235; + 8'd1 : rd_data <= #1 16'd21903; + 8'd2 : rd_data <= #1 -16'd23385; + 8'd3 : rd_data <= #1 16'd19754; + 8'd4 : rd_data <= #1 -16'd19330; + 8'd5 : rd_data <= #1 16'd23809; + 8'd6 : rd_data <= #1 -16'd21479; + 8'd7 : rd_data <= #1 16'd21660; + 8'd8 : rd_data <= #1 -16'd22779; + 8'd9 : rd_data <= #1 16'd20360; + 8'd10 : rd_data <= #1 -16'd24928; + 8'd11 : rd_data <= #1 16'd18211; + 8'd12 : rd_data <= #1 -16'd20873; + 8'd13 : rd_data <= #1 16'd22266; + 8'd14 : rd_data <= #1 -16'd23022; + 8'd15 : rd_data <= #1 16'd20116; + 8'd16 : rd_data <= #1 -16'd22051; + 8'd17 : rd_data <= #1 -16'd4096; + 8'd18 : rd_data <= #1 16'd10606; + 8'd19 : rd_data <= #1 16'd28562; + 8'd20 : rd_data <= #1 -16'd30635; + 8'd21 : rd_data <= #1 -16'd12680; + 8'd22 : rd_data <= #1 16'd2022; + 8'd23 : rd_data <= #1 16'd19978; + 8'd24 : rd_data <= #1 -16'd17846; + 8'd25 : rd_data <= #1 16'd109; + 8'd26 : rd_data <= #1 16'd14811; + 8'd27 : rd_data <= #1 16'd32767; + 8'd28 : rd_data <= #1 -16'd26430; + 8'd29 : rd_data <= #1 -16'd8475; + 8'd30 : rd_data <= #1 16'd6227; + 8'd31 : rd_data <= #1 16'd24183; + 8'd32 : rd_data <= #1 -16'd23253; + 8'd33 : rd_data <= #1 16'd15012; + 8'd34 : rd_data <= #1 -16'd12934; + 8'd35 : rd_data <= #1 16'd25331; + 8'd36 : rd_data <= #1 -16'd26201; + 8'd37 : rd_data <= #1 16'd12064; + 8'd38 : rd_data <= #1 -16'd15882; + 8'd39 : rd_data <= #1 16'd22383; + 8'd40 : rd_data <= #1 -16'd22383; + 8'd41 : rd_data <= #1 16'd15882; + 8'd42 : rd_data <= #1 -16'd12064; + 8'd43 : rd_data <= #1 16'd26201; + 8'd44 : rd_data <= #1 -16'd25331; + 8'd45 : rd_data <= #1 16'd12934; + 8'd46 : rd_data <= #1 -16'd15012; + 8'd47 : rd_data <= #1 16'd23253; + 8'd48 : rd_data <= #1 -16'd20271; + 8'd49 : rd_data <= #1 -16'd16839; + 8'd50 : rd_data <= #1 16'd21616; + 8'd51 : rd_data <= #1 16'd25048; + 8'd52 : rd_data <= #1 -16'd26336; + 8'd53 : rd_data <= #1 -16'd22904; + 8'd54 : rd_data <= #1 16'd15550; + 8'd55 : rd_data <= #1 16'd18983; + 8'd56 : rd_data <= #1 -16'd16786; + 8'd57 : rd_data <= #1 -16'd13354; + 8'd58 : rd_data <= #1 16'd25101; + 8'd59 : rd_data <= #1 16'd28533; + 8'd60 : rd_data <= #1 -16'd22851; + 8'd61 : rd_data <= #1 -16'd19419; + 8'd62 : rd_data <= #1 16'd19035; + 8'd63 : rd_data <= #1 16'd22467; + 8'd64 : rd_data <= #1 -16'd22833; + 8'd65 : rd_data <= #1 16'd2818; + 8'd66 : rd_data <= #1 16'd2818; + 8'd67 : rd_data <= #1 16'd28469; + 8'd68 : rd_data <= #1 -16'd30389; + 8'd69 : rd_data <= #1 -16'd4738; + 8'd70 : rd_data <= #1 -16'd4738; + 8'd71 : rd_data <= #1 16'd20913; + 8'd72 : rd_data <= #1 -16'd19361; + 8'd73 : rd_data <= #1 16'd6290; + 8'd74 : rd_data <= #1 16'd6290; + 8'd75 : rd_data <= #1 16'd31941; + 8'd76 : rd_data <= #1 -16'd26917; + 8'd77 : rd_data <= #1 -16'd1266; + 8'd78 : rd_data <= #1 -16'd1266; + 8'd79 : rd_data <= #1 16'd24385; + 8'd80 : rd_data <= #1 -16'd22589; + 8'd81 : rd_data <= #1 16'd19298; + 8'd82 : rd_data <= #1 -16'd19157; + 8'd83 : rd_data <= #1 16'd22730; + 8'd84 : rd_data <= #1 -16'd22926; + 8'd85 : rd_data <= #1 16'd18961; + 8'd86 : rd_data <= #1 -16'd19494; + 8'd87 : rd_data <= #1 16'd22393; + 8'd88 : rd_data <= #1 -16'd23063; + 8'd89 : rd_data <= #1 16'd18824; + 8'd90 : rd_data <= #1 -16'd19631; + 8'd91 : rd_data <= #1 16'd22256; + 8'd92 : rd_data <= #1 -16'd23400; + 8'd93 : rd_data <= #1 16'd18487; + 8'd94 : rd_data <= #1 -16'd19968; + 8'd95 : rd_data <= #1 16'd21919; + 8'd96 : rd_data <= #1 -16'd21137; + 8'd97 : rd_data <= #1 -16'd10818; + 8'd98 : rd_data <= #1 16'd17128; + 8'd99 : rd_data <= #1 16'd27447; + 8'd100 : rd_data <= #1 -16'd29317; + 8'd101 : rd_data <= #1 -16'd18998; + 8'd102 : rd_data <= #1 16'd8947; + 8'd103 : rd_data <= #1 16'd19266; + 8'd104 : rd_data <= #1 -16'd16885; + 8'd105 : rd_data <= #1 -16'd6566; + 8'd106 : rd_data <= #1 16'd21380; + 8'd107 : rd_data <= #1 16'd31699; + 8'd108 : rd_data <= #1 -16'd25066; + 8'd109 : rd_data <= #1 -16'd14747; + 8'd110 : rd_data <= #1 16'd13199; + 8'd111 : rd_data <= #1 16'd23518; + 8'd112 : rd_data <= #1 -16'd23291; + 8'd113 : rd_data <= #1 16'd9367; + 8'd114 : rd_data <= #1 -16'd5335; + 8'd115 : rd_data <= #1 16'd27322; + 8'd116 : rd_data <= #1 -16'd28806; + 8'd117 : rd_data <= #1 16'd3851; + 8'd118 : rd_data <= #1 -16'd10851; + 8'd119 : rd_data <= #1 16'd21807; + 8'd120 : rd_data <= #1 -16'd21019; + 8'd121 : rd_data <= #1 16'd11639; + 8'd122 : rd_data <= #1 -16'd3063; + 8'd123 : rd_data <= #1 16'd29594; + 8'd124 : rd_data <= #1 -16'd26534; + 8'd125 : rd_data <= #1 16'd6123; + 8'd126 : rd_data <= #1 -16'd8579; + 8'd127 : rd_data <= #1 16'd24079; + 8'd128 : rd_data <= #1 -16'd21235; + 8'd129 : rd_data <= #1 16'd21903; + 8'd130 : rd_data <= #1 -16'd23385; + 8'd131 : rd_data <= #1 16'd19754; + 8'd132 : rd_data <= #1 -16'd19330; + 8'd133 : rd_data <= #1 16'd23809; + 8'd134 : rd_data <= #1 -16'd21479; + 8'd135 : rd_data <= #1 16'd21660; + 8'd136 : rd_data <= #1 -16'd22779; + 8'd137 : rd_data <= #1 16'd20360; + 8'd138 : rd_data <= #1 -16'd24928; + 8'd139 : rd_data <= #1 16'd18211; + 8'd140 : rd_data <= #1 -16'd20873; + 8'd141 : rd_data <= #1 16'd22266; + 8'd142 : rd_data <= #1 -16'd23022; + 8'd143 : rd_data <= #1 16'd20116; + 8'd144 : rd_data <= #1 -16'd22051; + 8'd145 : rd_data <= #1 -16'd4096; + 8'd146 : rd_data <= #1 16'd10606; + 8'd147 : rd_data <= #1 16'd28562; + 8'd148 : rd_data <= #1 -16'd30635; + 8'd149 : rd_data <= #1 -16'd12680; + 8'd150 : rd_data <= #1 16'd2022; + 8'd151 : rd_data <= #1 16'd19978; + 8'd152 : rd_data <= #1 -16'd17846; + 8'd153 : rd_data <= #1 16'd109; + 8'd154 : rd_data <= #1 16'd14811; + 8'd155 : rd_data <= #1 16'd32767; + 8'd156 : rd_data <= #1 -16'd26430; + 8'd157 : rd_data <= #1 -16'd8475; + 8'd158 : rd_data <= #1 16'd6227; + 8'd159 : rd_data <= #1 16'd24183; + 8'd160 : rd_data <= #1 -16'd23253; + 8'd161 : rd_data <= #1 16'd15012; + 8'd162 : rd_data <= #1 -16'd12934; + 8'd163 : rd_data <= #1 16'd25331; + 8'd164 : rd_data <= #1 -16'd26201; + 8'd165 : rd_data <= #1 16'd12064; + 8'd166 : rd_data <= #1 -16'd15882; + 8'd167 : rd_data <= #1 16'd22383; + 8'd168 : rd_data <= #1 -16'd22383; + 8'd169 : rd_data <= #1 16'd15882; + 8'd170 : rd_data <= #1 -16'd12064; + 8'd171 : rd_data <= #1 16'd26201; + 8'd172 : rd_data <= #1 -16'd25331; + 8'd173 : rd_data <= #1 16'd12934; + 8'd174 : rd_data <= #1 -16'd15012; + 8'd175 : rd_data <= #1 16'd23253; + 8'd176 : rd_data <= #1 -16'd20271; + 8'd177 : rd_data <= #1 -16'd16839; + 8'd178 : rd_data <= #1 16'd21616; + 8'd179 : rd_data <= #1 16'd25048; + 8'd180 : rd_data <= #1 -16'd26336; + 8'd181 : rd_data <= #1 -16'd22904; + 8'd182 : rd_data <= #1 16'd15550; + 8'd183 : rd_data <= #1 16'd18983; + 8'd184 : rd_data <= #1 -16'd16786; + 8'd185 : rd_data <= #1 -16'd13354; + 8'd186 : rd_data <= #1 16'd25101; + 8'd187 : rd_data <= #1 16'd28533; + 8'd188 : rd_data <= #1 -16'd22851; + 8'd189 : rd_data <= #1 -16'd19419; + 8'd190 : rd_data <= #1 16'd19035; + 8'd191 : rd_data <= #1 16'd22467; + 8'd192 : rd_data <= #1 -16'd22833; + 8'd193 : rd_data <= #1 16'd2818; + 8'd194 : rd_data <= #1 16'd2818; + 8'd195 : rd_data <= #1 16'd28469; + 8'd196 : rd_data <= #1 -16'd30389; + 8'd197 : rd_data <= #1 -16'd4738; + 8'd198 : rd_data <= #1 -16'd4738; + 8'd199 : rd_data <= #1 16'd20913; + 8'd200 : rd_data <= #1 -16'd19361; + 8'd201 : rd_data <= #1 16'd6290; + 8'd202 : rd_data <= #1 16'd6290; + 8'd203 : rd_data <= #1 16'd31941; + 8'd204 : rd_data <= #1 -16'd26917; + 8'd205 : rd_data <= #1 -16'd1266; + 8'd206 : rd_data <= #1 -16'd1266; + 8'd207 : rd_data <= #1 16'd24385; + 8'd208 : rd_data <= #1 -16'd22589; + 8'd209 : rd_data <= #1 16'd19298; + 8'd210 : rd_data <= #1 -16'd19157; + 8'd211 : rd_data <= #1 16'd22730; + 8'd212 : rd_data <= #1 -16'd22926; + 8'd213 : rd_data <= #1 16'd18961; + 8'd214 : rd_data <= #1 -16'd19494; + 8'd215 : rd_data <= #1 16'd22393; + 8'd216 : rd_data <= #1 -16'd23063; + 8'd217 : rd_data <= #1 16'd18824; + 8'd218 : rd_data <= #1 -16'd19631; + 8'd219 : rd_data <= #1 16'd22256; + 8'd220 : rd_data <= #1 -16'd23400; + 8'd221 : rd_data <= #1 16'd18487; + 8'd222 : rd_data <= #1 -16'd19968; + 8'd223 : rd_data <= #1 16'd21919; + 8'd224 : rd_data <= #1 -16'd21137; + 8'd225 : rd_data <= #1 -16'd10818; + 8'd226 : rd_data <= #1 16'd17128; + 8'd227 : rd_data <= #1 16'd27447; + 8'd228 : rd_data <= #1 -16'd29317; + 8'd229 : rd_data <= #1 -16'd18998; + 8'd230 : rd_data <= #1 16'd8947; + 8'd231 : rd_data <= #1 16'd19266; + 8'd232 : rd_data <= #1 -16'd16885; + 8'd233 : rd_data <= #1 -16'd6566; + 8'd234 : rd_data <= #1 16'd21380; + 8'd235 : rd_data <= #1 16'd31699; + 8'd236 : rd_data <= #1 -16'd25066; + 8'd237 : rd_data <= #1 -16'd14747; + 8'd238 : rd_data <= #1 16'd13199; + 8'd239 : rd_data <= #1 16'd23518; + 8'd240 : rd_data <= #1 -16'd23291; + 8'd241 : rd_data <= #1 16'd9367; + 8'd242 : rd_data <= #1 -16'd5335; + 8'd243 : rd_data <= #1 16'd27322; + 8'd244 : rd_data <= #1 -16'd28806; + 8'd245 : rd_data <= #1 16'd3851; + 8'd246 : rd_data <= #1 -16'd10851; + 8'd247 : rd_data <= #1 16'd21807; + 8'd248 : rd_data <= #1 -16'd21019; + 8'd249 : rd_data <= #1 16'd11639; + 8'd250 : rd_data <= #1 -16'd3063; + 8'd251 : rd_data <= #1 16'd29594; + 8'd252 : rd_data <= #1 -16'd26534; + 8'd253 : rd_data <= #1 16'd6123; + 8'd254 : rd_data <= #1 -16'd8579; + 8'd255 : rd_data <= #1 16'd24079; + endcase // case(rd_addr) + end //if (strobe) + assign out_data[15:0]=reg_quadrant?-rd_data:rd_data; + sign_extend #(16,18) + ext_output (.in(out_data),.out(ext_out_data)); + +endmodule // rrc_coeff_ram_generated_1 + +//bw= 11 data_size= 1 abs_max= 649 len= 1 +module rrc_coeff_ram_generated1_2 (input clock, input strobe, input [3:0] phase, input [0:0] in_data, output [10:0] out_data,output [17:0] ext_out_data); + +reg reg_quadrant; +wire quadrant=in_data[0]; +wire [3:0] rd_addr=phase; +reg [10:0] rd_data; + + always @(posedge clock) + if (strobe) + begin + reg_quadrant <= #1 quadrant; + case (rd_addr) + 4'd0 : rd_data <= #1 11'd347; + 4'd1 : rd_data <= #1 -11'd460; + 4'd2 : rd_data <= #1 11'd168; + 4'd3 : rd_data <= #1 -11'd649; + 4'd4 : rd_data <= #1 -11'd250; + 4'd5 : rd_data <= #1 11'd298; + 4'd6 : rd_data <= #1 -11'd607; + 4'd7 : rd_data <= #1 -11'd26; + 4'd8 : rd_data <= #1 11'd347; + 4'd9 : rd_data <= #1 -11'd460; + 4'd10 : rd_data <= #1 11'd168; + 4'd11 : rd_data <= #1 -11'd649; + 4'd12 : rd_data <= #1 -11'd250; + 4'd13 : rd_data <= #1 11'd298; + 4'd14 : rd_data <= #1 -11'd607; + 4'd15 : rd_data <= #1 -11'd26; + endcase // case(rd_addr) + end //if (strobe) + assign out_data[10:0]=reg_quadrant?-rd_data:rd_data; + sign_extend #(11,18) + ext_output (.in(out_data),.out(ext_out_data)); + +endmodule // rrc_coeff_ram_generated_2 + +//bw_memory [4, 4, 0] data_size 5 +module frac_interp_1 + + (input clock, input reset, input enable, + output reg strobe_in, input strobe_out, + input wire [4:0] tx_shift, + input wire [15:0] signal_in, + output reg [15:0] signal_out); + +reg [3:0] phase;//max 16 phases + +reg [3:0] in_count;//16 bits in every register + +reg [15:0] input_16; + +reg [15:0] shift_16_0; +wire get_bit= (phase==4'd1) || (phase==4'd3) || (phase==4'd4) || (phase==4'd6) || (phase==4'd7) || (phase==4'd9) || (phase==4'd11) || (phase==4'd12) || (phase==4'd14) || (phase==4'd15); + + always @(posedge clock) + if (reset) + begin + strobe_in <= #1 0;// Reset + in_count <=#1 0; + input_16 <= #1 0; + + shift_16_0 <= #1 0; + + end //if (reset) + else //if (reset) + begin + if(enable & strobe_out & get_bit & (in_count == 4'd15)) + strobe_in <=#1 1'd1;//Only works if output of previous stage is registered and only updates on this strobe_in + else // if(strobe_in) //input a new 16 bit word and shift all regs 16 bit to the right= to next register) + strobe_in <= #1 0;//notice the else is always executed, even if there is no strobe_out so strobe_in will only be high for 1 clock + + if (enable & strobe_out) + begin + if ( get_bit) + + begin //shift input 1 bit to the left + if(in_count == 4'd15) //(strobe_in) //if(in_count == 4'd0) + begin + //strobe_in <=#1 1'd1;//Only works if output of previous stage is registered and only updates on this strobe_in + input_16 <= #1 signal_in; + end //if(in_count == 4'd0) + else //if(in_count == 4'd0) + begin + input_16 <= #1 {1'd0,input_16[15:1]};//just shift right //MDVH 14feb2007 + //input_16 <= #1 {input_16[14:0],1'd0};//just shift left //MDVH 14feb2007 + end // if(in_count == 4'd0) else + //shift_16_0 <= #1 {shift_16_0[14:0],input_16[15]};//MDVH 14feb2007 + shift_16_0 <= #1 {input_16[0],shift_16_0[15:1]};//MDVH 14feb2007 + + + in_count <= #1 in_count+4'd1; + end //if ((phase==.... + end //if (enable & strobe_out) + end // if (reset) else + + always @(posedge clock) + if (reset) + phase <=#1 0; + else if (enable & strobe_out) + phase <=#1 phase + 4'd1;//phase will roll-over to zero and start again + + +wire [4:0] data_0; +wire [4:0] data_1; +wire [0:0] data_2; +assign data_2=shift_16_0[10:10]; +assign data_1=shift_16_0[9:5]; +assign data_0=shift_16_0[4:0]; +wire [17:0] sum_0; +wire [17:0] sum_1; +wire [17:0] sum_2; +wire [17:0] sum_3; +assign sum_3=0; +reg [17:0] sum_all; + +//wire [15:0] sum_all_16bit; + + rrc_coeff_ram_generated1_0 rrc_coeff_ram_0 ( .clock(clock),.strobe(strobe_out),.phase(phase),.in_data(data_0),.out_data(),.ext_out_data(sum_0) ); + rrc_coeff_ram_generated1_1 rrc_coeff_ram_1 ( .clock(clock),.strobe(strobe_out),.phase(phase),.in_data(data_1),.out_data(),.ext_out_data(sum_1) ); + rrc_coeff_ram_generated1_2 rrc_coeff_ram_2 ( .clock(clock),.strobe(strobe_out),.phase(phase),.in_data(data_2),.out_data(),.ext_out_data(sum_2) ); +//assign sum_all= sum_0 + sum_1 + sum_2; +reg [17:0] sum_01; +reg [17:0] sum_23; +reg [17:0] sum_0123; + + always @(posedge clock) + if (reset) + begin + + sum_01 <= #1 0; + sum_23 <= #1 0; + sum_0123 <= #1 0; + + sum_all <=#1 0; + signal_out <= #1 0; + end + else if (enable & strobe_out) + begin + + sum_01 <= #1 sum_0+sum_1; + sum_23 <= #1 sum_2+sum_3; + sum_0123 <= #1 sum_01+sum_23; + sum_all <= #1 sum_0123; + + case(tx_shift) + //5'd0 : signal_out <= #1 round_16(sum_all);//no gain reduce + 5'd0 : signal_out <= #1 { sum_all[16:1] + (sum_all[17] & ( sum_all[0] )) }; + 5'd1 : signal_out <= #1 { sum_all[17:2] + (sum_all[17] & (|sum_all[1:0])) }; + 5'd2 : signal_out <= #1 { {{(1){sum_all[17]}}, sum_all[17:3]} + (sum_all[17] & (|sum_all[2:0])) }; + 5'd3 : signal_out <= #1 { {{(2){sum_all[17]}}, sum_all[17:4]} + (sum_all[17] & (|sum_all[3:0])) }; + 5'd4 : signal_out <= #1 { {{(3){sum_all[17]}}, sum_all[17:5]} + (sum_all[17] & (|sum_all[4:0])) }; + 5'd5 : signal_out <= #1 { {{(4){sum_all[17]}}, sum_all[17:6]} + (sum_all[17] & (|sum_all[5:0])) }; + 5'd6 : signal_out <= #1 { {{(5){sum_all[17]}}, sum_all[17:7]} + (sum_all[17] & (|sum_all[6:0])) }; + 5'd7 : signal_out <= #1 { {{(6){sum_all[17]}}, sum_all[17:8]} + (sum_all[17] & (|sum_all[7:0])) }; + 5'd8 : signal_out <= #1 { {{(7){sum_all[17]}}, sum_all[17:9]} + (sum_all[17] & (|sum_all[8:0])) }; + 5'd9 : signal_out <= #1 { {{(8){sum_all[17]}}, sum_all[17:10]} + (sum_all[17] & (|sum_all[9:0])) }; + 5'd10 : signal_out <= #1 { {{(9){sum_all[17]}},sum_all[17:11]} + (sum_all[17] & (|sum_all[10:0]))}; + 5'd11 : signal_out <= #1 { {{(10){sum_all[17]}},sum_all[17:12]} + (sum_all[17] & (|sum_all[11:0]))}; + 5'd12 : signal_out <= #1 { {{(11){sum_all[17]}},sum_all[17:13]} + (sum_all[17] & (|sum_all[12:0]))}; + 5'd13 : signal_out <= #1 { {{(12){sum_all[17]}},sum_all[17:14]} + (sum_all[17] & (|sum_all[13:0]))}; + 5'd14 : signal_out <= #1 { {{(13){sum_all[17]}},sum_all[17:15]} + (sum_all[17] & (|sum_all[14:0]))}; + 5'd15 : signal_out <= #1 { {{(14){sum_all[17]}},sum_all[17:16]} + (sum_all[17] & (|sum_all[15:0]))}; + + -5'd1 : signal_out <= #1 {sum_all[15:0] }; + -5'd2 : signal_out <= #1 {sum_all[14:0] ,{(1){1'b0}}}; + -5'd3 : signal_out <= #1 {sum_all[13:0] ,{(2){1'b0}}}; + -5'd4 : signal_out <= #1 {sum_all[12:0] ,{(3){1'b0}}}; + -5'd5 : signal_out <= #1 {sum_all[11:0] ,{(4){1'b0}}}; + -5'd6 : signal_out <= #1 {sum_all[10:0] ,{(5){1'b0}}}; + -5'd7 : signal_out <= #1 {sum_all[9:0] ,{(6){1'b0}}}; + -5'd8 : signal_out <= #1 {sum_all[8:0] ,{(7){1'b0}}}; + -5'd9 : signal_out <= #1 {sum_all[7:0] ,{(8){1'b0}}}; + -5'd10 : signal_out <= #1 {sum_all[6:0] ,{(9){1'b0}}}; + -5'd11 : signal_out <= #1 {sum_all[5:0] ,{(10){1'b0}}}; + -5'd12 : signal_out <= #1 {sum_all[4:0] ,{(11){1'b0}}}; + -5'd13 : signal_out <= #1 {sum_all[3:0] ,{(12){1'b0}}}; + -5'd14 : signal_out <= #1 {sum_all[2:0] ,{(13){1'b0}}}; + -5'd15 : signal_out <= #1 {sum_all[1:0] ,{(14){1'b0}}}; + + default : signal_out <= #1 { sum_all[16:1] + (sum_all[17] & ( sum_all[0] )) }; + //signal_out <= #1 { sum_all[17:2] + (sum_all[17] & (|sum_all[1:0])) }; + endcase // case(shift) + + //sum_all_14bit <= #1 sum_0123[16:3] + (sum_0123[16] & |sum_0123[2:0]);//round to 14 bit (reduce gain by 2 bit = 12 dB) + + //signal_out <= #1 round_16(sum_all);//no gain reduce + //signal_out <= #1 {{(2){sum_all_14bit[13]}},sum_all_14bit};//sign_extend to 16 bit (gain reduced by 2 bit = 12 dB) + + end //else if (enable & strobe_out) + + +/*assign sum_all_16bit=round_16(sum_all); +//register the output to ease timing of the DDR DAC output + always @(posedge clock or posedge reset) + if (reset) + signal_out <= #1 0; // Reset + else + signal_out <= #1 sum_all_16bit; +*/ +//round to 16 bit +// function [15:0] round_16; +// input [16:0] in_val; +// round_16 = in_val[16:1] + (in_val[16] & |in_val[0]);//round_16 = in_val[16:1] + (in_val[16] & in_val[0]) +// endfunction // round_16 + + +endmodule //module frac_interp_1 Index: usrp/fpga/sdr_lib/generate_frac_interp_05nov2007.py =================================================================== --- usrp/fpga/sdr_lib/generate_frac_interp_05nov2007.py (revision 0) +++ usrp/fpga/sdr_lib/generate_frac_interp_05nov2007.py (revision 0) @@ -0,0 +1,832 @@ +#!/usr/bin/env python + +import Numeric +import random +from gnuradio import gr, eng_notation +import math +from math import cos,sin +import Numeric +import sys +import datetime + +from gnuradio.eng_option import eng_option +from optparse import OptionParser + +from Numeric import zeros + +from operator import add, mul + + + + +def flatten(in_data): + """returns a single flat list with the elements of every contained list or tuple in in_data""" + result = [] + for element in in_data: + if hasattr(element, "__len__"): + result.extend(flatten(element)) + else: + result.append(element) + return result + +def abs_max_reclist(in_data): + """returns the absolute maximum of the elements in every recursive list in in_data""" + flat_data=flatten(in_data) + return max(max(flat_data),abs(min(flat_data))) + +def max_reclist(in_data): + """returns the maximum of the elements in every recursive list in in_data""" + flat_data=flatten(in_data) + return max(flat_data) + +def min_reclist(in_data): + """returns the minimum of the elements in every recursive list in in_data""" + flat_data=flatten(in_data) + return min(flat_data) + +def sum_reclist(in_data): + """returns the sum of the elements in every recursive list in in_data""" + flat_data=flatten(in_data) + return reduce(add, flat_data) + + + + + +def root_raised_cosine (gain, sampling_freq, symbol_rate, alpha, ntaps,mu,do_scale=False,do_scale_abs=False): + ntaps2 = int(ntaps) #ensure that ntaps is an integer + ntaps3=ntaps2 + if ntaps3%2==0: + ntaps3=ntaps3+1 + if ntaps3 != ntaps: + print "//ntaps is not odd, exiting" + #sys.exit(0) + #else: + ntaps=ntaps2 + #ntaps = ntaps | 1 # ensure that ntaps is odd + + M_PI=math.pi + spb = float(sampling_freq)/float(symbol_rate)# samples per bit/symbol + #??vector taps(ntaps); + taps=[] + for i in range(ntaps): + taps.append(0.0) + #print "//ZERO taps",taps + scale = 0.0 + scale_abs = 0.0 + num=0.0 + den=0.0 + x1=0.0 + x2=0.0 + x3=0.0 + xindx=0.0 + xindx2=0.0 + for i in range (ntaps): #(int i=0;i0: + incr_list.append(j) #TODO or should this be j+1 (where 16 whould be 0) + d_mu=s-f + ii=ii+incr + oo=oo+1 + #print"//incr_list",incr_list + if do_scale: + scale=1.0 + if do_scale_abs: + scale=abs_max_reclist(rrc_taps) + else: + scale=sum_reclist(rrc_taps) + for j in range(nfilters): + for k in range(ntaps_per_filter): + rrc_taps[j][k]=gain*rrc_taps[j][k]/scale + for i in range(nfilters): + print "//poly_filter[",i,"] = " + print "//",rrc_taps[i] + print + #rrc_taps.reverse() #MDVH 14feb2007 removed # to re-enable this. Later disabled it again + #raise SystemExit, 1 + return rrc_taps, incr_list + + +def generate_summed_taps_memory(all_taps,data_size,num,offset): + sums_float=[] + abs_max=-1.0 + address_bits_not_used=0 + int_offset=offset + nfilters=len(all_taps) + ntaps_per_filter=len(all_taps[0]) + if (offset<0): + address_bits_not_used=-offset + int_offset=0 # = offset+address_bits_not_used + elif (offset+data_size>ntaps_per_filter): + address_bits_not_used=offset+data_size-ntaps_per_filter + int_offset=offset #-address_bits_not_used + else: + address_bits_not_used=0 + int_offset=offset + + address_bits=data_size-address_bits_not_used-1 #The -1 is because we imply that the next databit is zero and use symmetry if not + #print "//address_bits",address_bits + #print "//address_bits_not_used",address_bits_not_used + #print "//offset", offset + #print "//int_offset",int_offset + #print "//1<=0) & (indexabs_max): + abs_max=abs(mac) + + #sum_16bit=round(32767.0*mac/scale) + # if(abs(sum_16bit)>abs_max_16bit): + # abs_max_16bit=abs(sum_16bit) + # signed_max_16bit=max(signed_max_16bit,sum_16bit) + # signed_min_16bit=min(signed_min_16bit,sum_16bit) + return sums_float,abs_max,address_bits + +def generate_summed_taps_memories(all_taps,gain,data_size): + sums_floats=[] + abs_max=-1.0 + ntaps_per_filter=len(all_taps[0]) + nfilters=len(all_taps) + bits_per_memory=data_size + real_bits_per_memory=bits_per_memory-1 + num_memories=int(math.ceil(float(ntaps_per_filter)/float(bits_per_memory))) + address_bits=[] + for i in range(num_memories): + offset=i*bits_per_memory + tmp_sums_float,tmp_abs_max,real_used_data_size=generate_summed_taps_memory(all_taps,data_size,i,offset) + address_bits.append(real_used_data_size) + sums_floats.append(tmp_sums_float) + abs_max=max(abs_max,tmp_abs_max) + sums_16bits=[] + abs_max_16bit=-1 + signed_max_16bit=-1 + signed_min_16bit=1 + for i in range(num_memories): + sums_16bits.append([]) + for j in range(nfilters): + sums_16bits[i].append([]) + for k in range(1<ntaps): + address_bits_not_used=offset+data_size-ntaps + int_offset=offset #-address_bits_not_used + else: + address_bits_not_used=0 + int_offset=offset + + address_bits=data_size-address_bits_not_used-1 #The -1 is because we imply that the next databit is zero and use symmetry if not + #print "//address_bits",address_bits + #print "//address_bits_not_used",address_bits_not_used + #print "//offset", offset + #print "//int_offset",int_offset + #print "//1<=0) & (indexabs_max_16bit): + abs_max_16bit=abs(sum_16bit) + signed_max_16bit=max(signed_max_16bit,sum_16bit) + signed_min_16bit=min(signed_min_16bit,sum_16bit) + if(print_txt): + print i,int(sum_16bit) + print i,mac + if(print_verilog): + #print '%(language)s has %(#)03d quote types.' % \ + # {'language': "Python", "#": 2} + if(sum_16bit<0): + sign=-1 + else: + sign=1 + print " 8'd%i : rd_data <= #1 %i'd%i;" % (((mu_index<<(data_size-1)) | i),sign*bw,abs(sum_16