The verilog code for the fractional interpolating Root-Raised-Cosine filter is generated by a script.
usrp/fpga/sdr_lib/generate_frac_interp_05nov2007.py

With this script you can generate code for any fractional interpolation factor and any alpha value (for the RRC)

The symbolrate you get is 32*decimation/interpolation Mbit/sec
The bitrate you get for QPSK is 2*symbolrate 
The bandwith you use is (1.0+alpha)*symbolrate

decimation is 1 to 16
interpolation is 1 to 16

To get instructions just call:
  generate_frac_interp_05nov2007.py --help

By generating your own code you can  choose your needed bitrate and alpha value.

There is also a script which generates all files needed to build the 4 rbfs which are already in this distribution. 
usrp/fpga/sdr_lib/generate_all_frac_interp_files.sh
You can look in this script to see examples on how to use generate_frac_interp_05nov2007.py

When you run it you get:
  Generating code for fractional interpolating Root-Raised_Cosine filters in verilog for USRP
  Generating verilog files for both I and Q channels for alpha 0.2 and 0.35 and for 4 Mbit and 40 Mbit
  *int16_dec10*.v are for 40 Mbit QPSK and *int16_dec1*.v are for 4 Mbit QPSK
  done
  For bitrate=40 Mbit/sec and alpha=0.35 use the following two files
  frac_interp_alpha0.35_int16_dec10_DACint4X_chan0.v
  frac_interp_alpha0.35_int16_dec10_DACint4X_chan1.v
  For bitrate=4 Mbit/sec and alpha=0.35 use the following two files
  frac_interp_alpha0.35_int16_dec1_DACint4X_chan0.v
  frac_interp_alpha0.35_int16_dec1_DACint4X_chan1.v
  For bitrate=40 Mbit/sec and alpha=0.2 use the following two files
  frac_interp_alpha0.2_int16_dec10_DACint4X_chan1.v
  frac_interp_alpha0.2_int16_dec10_DACint4X_chan0.v
  For bitrate=4 Mbit/sec and alpha=0.2 use the following two files
  frac_interp_alpha0.2_int16_dec1_DACint4X_chan0.v
  frac_interp_alpha0.2_int16_dec1_DACint4X_chan1.v
  Copy the two files to usrp/fpga/sdr_lib/frac_interp_0.v and frac_interp_1.v
  After copying the two files, build the rbf file with the Altera Quartus II software.
  Make sure you use this special patched usrp sourcetree for usrp_qpsk. At the moment the standard usrp sourctree doesn't know about these files
  Written by Martin Dudok van Heel, 2007
  Olifantasia

With these files the following rbs are built:
usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec10_DACint4X.rbf	bitrate= 40Mbit/sec, alpha=0.2
usrp_frac_interp_2rxhb_2tx_alpha0.2_int16_dec1_DACint4X.rbf     bitrate= 4 Mbit/sec, alpha=0.2
usrp_frac_interp_2rxhb_2tx_alpha0.35_int16_dec10_DACint4X.rbf   bitrate= 40 Mbit/sec, alpha=0.35
usrp_frac_interp_2rxhb_2tx_alpha0.35_int16_dec1_DACint4X.rbf    bitrate= 4 Mbit/sec, alpha=0.35


usrp/fpga/sdr_lib/generate_frac_interp_05nov2007.py --help
usage: generate_frac_interp_05nov2007.py: [options]

options:
  -h, --help            show this help message and exit
  -c CHANNEL, --channel=CHANNEL
                        set which channel to generate (0 or 1) [default=0]
  -n NTAPS_PER_FILTER, --ntaps-per-filter=NTAPS_PER_FILTER
                        set number of taps per interpolation phase
                        [default=11]
  -d DECIMATION, --decimation=DECIMATION
                        set rrc decimation rate to DECIM [default=10]
  -i INTERPOLATION, --interpolation=INTERPOLATION
                        set rrc decimation rate to INTERP [default=16]
  -a ALPHA, --alpha=ALPHA
                        set rrc alpha to ALPHA (default=0.35.) (Common used
                        values are 0.15, 0.2 and 0.35)
  -D DATA_SIZE, --data-size=DATA_SIZE
                        number of bits used for data per memory. (default=5)
                        (This has nothing to do with precision, but all with
                        the size of ramblocks in the fpga)
  -P PHASE_SIZE, --phase-size=PHASE_SIZE
                        number of bits used for interpolation phases.
                        (default=4) (This has nothing to do with precision,
                        but all with the size of ramblocks in the fpga)


Written by Martin Dudok van Heel, 2007
Olifantasia