Usrp 8 Bit samples 

These patches add a new mode to the usrp fpga firmware, usrp driver and gr-usrp gnuradio driver..
This new mode only sends 8 bit samples over the usb bus in stead of 16.
It truncates the samples by discarding the 8 least significant bits.
That is why the new mode is called FPGA_MODE_TRUNC_TO_8BIT.

The reason for this code is to be able to get higher samplerates or more channels at the same time over the usb bus.
Depending on the speed of your usb card and mainbord you can get between 16 MB/sec and 32 MB/sec over the usb bus.
Using 16 bit comples samples this means in the default 16 bit mode you can get a maximum of 1 channel: 8 Msamples/sec  or 2 channels 4 Msamples/sec.
Using only 8 bit samples doubles this rate to 1 channel 16 Msamples/sec or 2 channels 8 Msamples/sec.

This is my first verilog code so there could be bugs in there or I could have overlooked some consequences of the changes.

The first tests I did with the new code I did get 8 bit samples and it looked quite like I expected.
(Although I still miss samples at higher sample rates (lower decimation factors), even when just dumping to a ramdisk)

The one feature that is still missing is the ability to tell the usrp to shift the bits of the samples.
With only the 8 most significant bits you can only see very strong signals. Weak signals come out as just zero.
I hoped the pga gain setting would be enough to get the top 8 bits saturated but this is not the case.

It should be possible to implement a function in the firmware and a parameter in the driver which shifts the bits of the samples to the left but keep the sign bit.
This would be an extra a kind of gain setting with 6 dB steps.
Then you can increase this shift value untill your signal gets saturated/clamped.

I only implemented the 8 bit feature in the receive path.

You can try the code with the new usrp_oscope_c.py example I included.
It has an option --bitdepth which takes 8 or 16 as a value (default is 16)

The patches,example and firmware can be downloaded from:
http://www.olifantasia.com/pub/projects/gnuradio/mdvh/mypatches/usrp_8bit/

These patches alter the fpga sourcecode. You need the Quartus II web software from altera to build the firmware yourself.
I already build one for you, it is called usrp_fpga_8bit_3.rbf
You have to rename it to usrp_fpga.rbf and copy it to $PREFIX/share/usrp/rev2 to use it.
(Be sure to backup your original firmware.)

I am quite happy I did not burnup my usrp when I built and uploaded this homebrew firmware.
But don't sew me when something breaks if you use this.


Greetings,
          Martin Dudok van Heel


Changes:
usrp:
2005-08-25  Martin Dudok van Heel  <nldudok1 at olifantasia.com>

	* firmware/include/fpga_regs_common.h,
          fpga/sdr_lib/rx_buffer.v, fpga/toplevel/usrp_std/usrp_std.v,
          host/apps/test_usrp_standard_rx.cc, host/lib/usrp_standard.cc, 
          host/lib/usrp_standard.h: added 8bit samples support
          (enable by using the new mode FPGA_MODE_TRUNC_TO_8BIT)

gr-usrp
2005-08-25  Martin Dudok van Heel  <nldudok1 at olifantasia.com>

	* src/usrp.py, src/usrp1.i, src/usrp1_source_base.cc, 
          src/usrp1_source_base.h, src/usrp1_source_c.cc, 
          src/usrp1_source_s.cc: added 8bit samples support
          (enable by using the new mode usrp.FPGA_MODE_TRUNC_TO_8BIT)